鈥?/div>
鈥?715 mW (military)
Super low standby power
鈥?Less than 165 mW when deselected
EPROM technology 100% programmable
Slim 300-mil package (7C271)
Direct replacement for bipolar PROMs
Capable of withstanding >2001V static discharge
low-power stand-by mode. The CY7C271 is packaged in the
300-mil slim package. The CY7C274 is packaged in the
industry standard 600-mil package. Both the CY7C271 and
CY7C274 are available in a cerDIP package equipped with an
erasure window to provide for reprogrammability. When
exposed to UV light, the PROM is erased and can be repro-
grammed. The memory cells utilize proven EPROM floating
gate technology and byte-wide intelligent programming
algorithms.
The CY7C271 and CY7C274 offer the advantage of lower
power, superior performance, and programming yield. The
EPROM cell requires only 12.5V for the super voltage, and low
current requirements allow for gang programming. The
EPROM cells allow each memory location to be tested 100%
because each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer
programming, the product will meet DC and AC specification
limits.
Reading the 7C271 is accomplished by placing active LOW
signals on CS
1
and CE, and an active HIGH on CS
2
. Reading the
7C274 is accomplished by placing active LOW signals on OE and
CE. The contents of the memory location addressed by the address
lines (A
0
鈭扐
14
) will become available on the output lines (O
0
鈭扥
7
).
Functional Description
The CY7C271 and CY7C274 are high-performance
32,768-word by 8-bit CMOS PROMs. When disabled (CE
HIGH), the 7C271/7C274 automatically powers down into a
Logic Block Diagram
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Y ADDRESS
X ADDRESS
256 x 1024
PROGRAMABLE
ARRAY
8 x 1 OF 128
MULTIPLEXER
Pin Configurations
DIP/Flatpack
O
7
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
O
3
GND
1
2
3
4
28
27
26
V
CC
A
10
A
11
A
12
A
13
A
14
CS
1
CS
2
CE
O
7
O
6
O
5
O
4
O
3
V
PP
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
DIP/Flatpack
1
2
3
4
28
27
26
V
CC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
O
6
O
5
O
4
O
3
O
6
O
5
25
5
24
6 7C271 23
22
7
21
8
9
10
11
12
13
14
20
19
18
17
16
15
25
5
24
6 7C274 23
22
7
21
8
9
10
11
12
13
14
20
19
18
17
16
15
O
4
LCC/PLCC (Opaque Only)
4 3 2 1 32 31 30
29
5
28
7C271
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
14151617 181920
O1
O2
GND
NC
O3
O4
O5
A7
A8
A9
NC
V
CC
A10
A11
O
2
LCC/PLCC (Opaque Only)
4 3 2 1 32 31 30
29
5
28
7C274
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
14151617 181920
O1
O2
GND
NC
O3
O4
O5
A7
A12
VPP
NC
V
CC
A14
A13
O
1
POWER-DOWN
O
0
CE
(7C271) CS
1
(7C271) CS
2
(7C274) OE
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
O
0
A
12
A
13
A
14
NC
CS
1
CS
2
CE
O
7
O
6
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
O
0
A
8
A
9
A
11
NC
OE
A
10
CE
O
7
O
6
Cypress Semiconductor Corporation
Document #: 38-04008 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 27, 2002
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