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CY7C225A-40LMB Datasheet

  • CY7C225A-40LMB

  • 512 x 8 Registered PROM

  • 9頁

  • CYPRESS

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1CY7C225A
CY7C225A
512 x 8 Registered PROM
Features
鈥?CMOS for optimum speed/power
鈥?High speed
鈥?25 ns address set-up
鈥?12 ns clock to output
鈥?Low power
鈥?495 mW (Commercial)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?660 mW (Military)
Synchronous and asynchronous output enables
On-chip edge-triggered registers
Buffered common PRESET and CLEAR inputs
EPROM technology, 100% programmable
Slim 300-mil, 24-pin plastic or hermetic DIP, 28-pin LCC,
or 28-pin PLCC
5V
鹵10%
V
CC
, commercial and military
TTL-compatible I/O
Direct replacement for bipolar PROMs
鈥?Capable of withstanding greater than 2001V static
discharge
Functional Description
The CY7C225A is a high-performance 512-word by 8-bit
electrically programmable read only memory packaged in a
slim 300-mil plastic or hermetic DIP, 28-pin leadless chip
carrier, and 28-pin PLCC. The memory cells utilize proven
EPROM floating gate technology and byte-wide intelligent
programming algorithms.
The CY7C225A replaces bipolar devices and offers the advan-
tages of lower power, superior performance, and high
programming yield. The EPROM cell requires only 12.5V for
the supervoltage and low current requirements allow for gang
programming. The EPROM cells allow for each memory
location to be tested 100%, as each location is written into,
erased, and repeatedly exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that
after customer programming the product will meet AC specifi-
cation limits.
Logic Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
ADDRESS
O
2
O
1
ADDRESS
DECODER
8-BIT
EDGE-
TRIGGERED
REGISTER
ROW
ADDRESS
PROGRAMMABLE
ARRAY
MULTIPLEXER
O
5
O
4
O
7
Pin Configurations
DIP
Top View
A
7
O
6
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
3
O
0
O
1
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
8
PS
E
CLR
E
S
CP
O
7
O
6
O
5
O
4
O
3
CLR
CP
A
4
A
3
A
2
A
1
A
0
NC
O
0
E
S
E
4 3 2 1 28 27 26
25
5
24
6
23
7
22
8
21
9
20
10
19
11
12 13 141516 17 18
O1
O2
GND
NC
O3
O4
O5
A5
A6
A7
NC
VCC
A8
PS
E
CLR
E
S
CP
NC
O
7
O
6
PS
S
R
CP
O
0
LCC/PLCC
Top View
Selection Guide
7C225A-25
Minimum Address Set-Up Time
Maximum Clock to Output
Maximum Operating
Current
Commercial
Military
25
12
90
7C225A-30
30
15
90
120
7C225A-40
40
25
Unit
ns
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-04001 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised October 8, 2002

CY7C225A-40LMB相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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