CY7C199N
32K x 8 Static RAM
Features
鈥?High speed
鈥?12 ns
鈥?Fast t
DOE
鈥?CMOS for optimum speed/power
鈥?Low active power
鈥?467 mW (max, 12 ns 鈥淟鈥?version)
鈥?Low standby power
鈥?0.275 mW (max, 鈥淟鈥?version)
鈥?2V data retention (鈥淟鈥?version only)
鈥?Easy memory expansion with CE and OE features
鈥?TTL-compatible inputs and outputs
鈥?Automatic power-down when deselected
Functional Description
The CY7C199N is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199NN is in
the standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location
addressed by the address present on the address pins (A
0
through A
14
). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Logic Block Diagram
Pin Configurations
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
DIP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
21
20
19
18
17
16
15
14
13
12
11
10
9
8
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
CE
WE
OE
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
1024 x 32 x 8
ARRAY
I/O
3
I/O
4
I/O
5
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
10
A
12
A
13
A
11
Selection Guide
-12
Maximum Access Time
Maximum Operating Current
L
Maximum CMOS Standby Current
L
Cypress Semiconductor Corporation
Document #: 001-06493 Rev. **
鈥?/div>
12
160
90
10
0.05
-15
15
155
90
10
0.05
鈥?/div>
-20
20
150
90
10
0.05
-25
25
150
80
10
0.05
-35
35
140
70
10
0.05
-55
55
140
70
10
0.05
mA
Unit
ns
mA
A
14
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
198 Champion Court
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised February 2, 2006
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