鈥?/div>
Fast access time: 12 ns, 15 ns, 20 ns, and 25 ns
Wide voltage range: 5.0V 鹵 10% (4.5V to 5.5V)
CMOS for optimum speed and power
TTL-compatible inputs and outputs
2.0V data retention
Low CMOS standby power
Automated power down when deselected
Available in Pb-free 28-pin TSOP I, 28-pin Molded SOJ and
28-pin DIP packages
General Description
[1]
The CY7C199CN is a high performance CMOS Asynchronous
SRAM organized as 32K by 8 bits that supports an
asynchronous memory interface. The device features an
automatic power down feature that reduces power
consumption when deselected.
See the
鈥淭ruth Table鈥?on page 3
in this data sheet for a
complete description of read and write modes.
The CY7C199CN is available in Pb-free 28-pin TSOP I, 28-pin
Molded SOJ and 28-pin DIP package(s).
Logic Block Diagram
Input Buffer
Row Decoder
RAM Array
Sense Amps
I/Ox
CE
Column Decoder
Power
Down
Circuit
WE
OE
X
A
X
Product Portfolio
鈥?2
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
(low power)
12
85
500
鈥?5
15
80
500
鈥?0
20
75
500
鈥?5
25
75
500
Unit
ns
mA
碌A(chǔ)
Note
1. For best practices recommendations, refer to the Cypress application note
System Design Guidelines
on
www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06435 Rev. *B
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised March 08, 2007
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