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CY7C198-25LMB Datasheet

  • CY7C198-25LMB

  • 32K x 8 Static RAM

  • 456.02KB

  • 9頁

  • CYPRESS

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7c198: 10/25/89
Revision: February 29, 1996
Features
D
D
D
D
D
D
D
High speed
15 ns
CMOS for optimum speed/power
Low active power
990 mW
Low standby power
195 mW
Easy memory expansion with CE and
OE features
TTL compatible inputs and outputs
Automatic power down when
deselected
The CY7C198 is a high performance
CMOS static RAM organized as 32,768
words by8bits.Easymemoryexpansionis
provided by an active LOW chip enable
(CE)andactiveLOWoutputenable(OE)
and three state drivers. This device has an
automatic power down feature, reducing
the power consumption by 80% when de
selected. The CY7C198 is available in a
600 mil wide cerDIP and LCC package
and a 32 lead TSOP package.
An active LOW write enable signal (WE)
controls the writing/reading operation of
the memory. When CE and WE inputs
arebothLOW,dataontheeightdatainput/
Functional Description
output pins (I/O
0
through I/O
7
) is written
intothememorylocationaddressedbythe
address present on the address pins (A
0
through A
14
). Reading the device is ac
complishedbyselectingthedeviceanden
abling the outputs, CE and OE active
LOW, while WE remains inactive or
HIGH. Under these conditions, the con
tents of the location addressed by the in
formationonaddresspinsispresentonthe
eight data input/output pins.
Theinput/outputpinsremaininahigh im
pedance state unless the chip is selected,
outputs are enabled, and write enable
(WE) is HIGH.
A die coat is used to ensure alpha immunity.
32K x 8 Static RAM
CY7C198
Logic Block Diagram
Pin Configurations
CerDIP
Top View
A
5
A
6
A
7
A
8
A
9
A
10
I/O
0
A
11
A
12
I/O
1
A
13
A
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
4
5
6
7
8
9
10
11
12
13
A7
A 12
A 14
V
CC
LCC
Top View
3
2
1 32 31 30
29
28
27
26
25
24
23
22
21
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
WE
NC
A
13
C198 1
INPUT BUFFER
A
0
ROW DECODER
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
I/O
0
I/O
2
SENSE AMPS
I/O
1
I/O
2
I/O
3
GND
14 15 16 17 1819 20
GND
I/O
1
I/O
2
NC
I/O
3
I/O
4
I/O
5
1024 x 32 x 8
ARRAY
C198 3
I/O
4
I/O
5
CE
WE
COLUMN
DECODER
OE
POWER
DOWN
I/O
6
I/O
7
A
10
A
11
A
12
A
13
A
14
C198 2
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA) Commercial
Military
Maximum Standby Current (mA)
7C198-15 7C198-20 7C198-25 7C198-35 7C198-45
15
Shaded area contains preliminary information.
Cypress Semiconductor Corporation
180
30
20
150
170
30
25
35
45
150
30
150
25
150
25
D
3901 North First Street
1
D
San Jose
CA 95134
D
408-943-2600
February 1988 - Revised February 1996
D

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