CY7C197N
256Kx1 Static RAM
Features
鈥?High speed
鈥?25 ns
鈥?CMOS for optimum speed/power
鈥?Low active power
鈥?880 mW
鈥?Low standby power
鈥?220 mW
鈥?TTL-compatible inputs and outputs
鈥?Automatic power-down when deselected
Functional Description
The CY7C197N is a high-performance CMOS static RAM
organized as 256K words by 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and three-state
drivers. The CY7C197N has an automatic power-down
feature, reducing the power consumption by 75% when
deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (D
IN
) is written into the memory location specified on
the address pins (A
0
through A
17
).
Reading the device is accomplished by taking chip enable
(CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified
on the address pins will appear on the data output (D
OUT
) pin.
The output pin stays in a high-impedance state when Chip
Enable (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C197N utilizes a die coat to insure alpha immunity.
Logic Block Diagram
DI
Pin Configurations
DIP
Top View
INPUT BUFFER
A
13
A
14
A
15
A
16
A
17
A
0
A
1
A
2
A
3
A
4
ROW DECODER
1024 x 256
ARRAY
SENSE AMPS
DO
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
D
OUT
WE
GND
1
24
2
23
22
3
4
21
5
20
6 7C197 19
18
7
8
17
9
16
10
15
14
11
12
13
V
CC
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
D
IN
CE
COLUMN
DECODER
POWER
DOWN
CE
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
WE
Selection Guide
-25
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
25
95
30
30
-45
45
Cypress Semiconductor Corporation
Document #: 001-06495 Rev. **
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised February 2, 2006
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