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Fast access time: 12 ns
Wide voltage range: 5.0V 鹵 10% (4.5V to 5.5V)
CMOS for optimum speed and power
TTL compatible inputs and outputs
Available in 24-lead DIP and 24-lead SOJ
General Description
[1]
The CY7C197BN is a high performance CMOS Asynchronous
SRAM organized as 256K 脳 1 bits that supports an
asynchronous memory interface. The device features an
automatic power down feature that significantly reduces power
consumption when deselected.
See the
鈥淭ruth Table鈥?on page 7
for a complete description of
Read and Write modes.
The CY7C197BN is available in 24-lead DIP and 24-lead SOJ
package(s).
Logic Block Diagram
Din
Input
Buffer
Row Decoder
RAM Array
Sense Amps
Dout
CE
Column
Decoder
Power
Down
Circuit
x
WE
A x
Product Portfolio
-12
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
12
150
10
-15
15
150
10
-25
25
95
10
Unit
ns
mA
mA
Notes
1. For best practice recommendations, refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06447 Rev. **
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198 Champion Court
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San Jose
,
CA 95134-1709
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408-943-2600
Revised March 21, 2007
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