CY7C197B
256 Kb (256K x 1) Static RAM
Features
鈥?Fast access time: 12 ns and 25 ns
鈥?Wide voltage range: 5.0V 鹵 10% (4.5V to 5.5V)
鈥?CMOS for optimum speed/power
鈥?TTL-compatible Inputs and Outputs
鈥?Available in 24 DIP and 24 SOJ
General Description
1
The CY7C197B is a high-performance CMOS Asynchronous
SRAM organized as 256K 脳 1 bits that supports an
asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected.
See the Truth Table in this data sheet for a complete
description of read and write modes.
The CY7C197B is available in 24 DIP and 24 SOJ package(s).
Logic Block Diagram
Din
Input
Buffer
Row Decoder
RAM
Array
Sense Amps
Dout
CE
Column
Decoder
Power
Down
Circuit
WE
x
A
x
Product Portfolio
12 ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
12
150
10
25 ns
25
95
10
Unit
ns
mA
mA
Notes:
1. For best-practice recommendations, please refer to the Cypress application note
System Design Guidelines
at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05410 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised September 15, 2003
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