CY7C194BN
256 Kb (64K x 4) Static RAM
Features
鈥?Fast access time: 15 ns and 25 ns
鈥?Wide voltage range: 5.0V 鹵 10% (4.5V to 5.5V)
鈥?CMOS for optimum speed/power
鈥?TTL-compatible inputs and outputs
鈥?CY7C194BN is available in 24 DIP, 24 SOJ packages.
General Description
[1]
The CY7C194BN is a high-performance CMOS
Asynchronous SRAM organized as 64K 脳 4 bits that supports
an asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected.
See the Truth Table in this data sheet for a complete
description of read and write modes.
The CY7C194BN is available in 24 DIP, 24 SOJ package(s).
Logic Block Diagram
Input Buffer
Row Decoder
RAM Array
Sense Amps
I/Ox
CE
Column Decoder
Power
Down
Circuit
WE
OE
(7C195 only)
X
A
X
Product Portfolio
-15
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
15
80
10
-25
25
80
10
Unit
ns
mA
mA
Notes:
1. For best-practice recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06446 Rev. **
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised February 1, 2006
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