CY7C194B
CY7C195B
256 Kb (64K x 4) Static RAM
Features
鈥?Fast access time: 12 ns, 15 ns, and 25 ns
鈥?Wide voltage range: 5.0V 鹵 10% (4.5V to 5.5V)
鈥?CMOS for optimum speed/power
鈥?TTL-compatible inputs and outputs
鈥?Available in 24 DIP, 24 SOJ, 28 DIP, and 28 SOJ
General Description
1
The CY7C194B-CY7C195B is a high-performance CMOS
Asynchronous SRAM organized as 64K 脳 4 bits that supports
an asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected. Output enable (OE) is
supported only in CY7C195B.
2
See the Truth Table in this data sheet for a complete
description of read and write modes.
The CY7C194B-CY7C195B is available in 24 DIP, 24 SOJ, 28
DIP, and 28 SOJ package(s).
Logic Block Diagram
Input Buffer
Row Decoder
RAM Array
Sense Amps
I/Ox
CE
Column Decoder
Power
Down
Circuit
WE
OE
(7C195 only)
X
A
X
Product Portfolio
12 ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes:
1. For best-practice recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. All OE-specific descriptions and parameters in this datasheet pertain to CY7C195 only.
15 ns
15
80
10
25 ns
25
80
10
Unit
ns
mA
mA
12
90
10
Cypress Semiconductor Corporation
Document #: 38-05409 Rev. *A
鈥?/div>
3901 North First Street
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San Jose
,
CA 95134
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408-943-2600
Revised September 17, 2003
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