1CY 7C15 12
PRELIMINARY
CY7C1512
64K x 8 Static RAM
Features
鈥?High speed
鈥?t
AA
= 15 ns
鈥?CMOS for optimum speed/power
鈥?Low active power
鈥?770 mW
鈥?Low standby power
鈥?28 mW
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Easy memory expansion with CE
1
, CE
2
, and OE options
and three-state drivers. This device has an automatic pow-
er-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking chip enable
one (CE
1
) and write enable (WE) inputs LOW and chip enable
two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
15
).
Reading from the device is accomplished by taking chip en-
able one (CE
1
) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C1512 is available in standard TSOP type I and
450-mil-wide plastic SOIC packages.
Functional Description
The CY7C1512 is a high-performance CMOS static RAM or-
ganized as 65,536 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
1
), an active
HIGH chip enable (CE
2
), an active LOW output enable (OE),
Logic Block Diagram
Pin Configurations
SOIC
Top View
NC
NC
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
NC
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
I/O
1
I/O
2
64K x 8
ARRAY
1512-2
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
I/O
3
I/O
4
I/O
5
POWER
DOWN
CE
1
CE
2
WE
COLUMN
DECODER
I/O
6
I/O
7
1512-1
TSOP I
Top View
(not to scale)
OE
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Commercial
Current (mA)
Maximum CMOS
Commercial
Standby Current (mA)
7C1512-15
15
140
5
7C1512-20
20
130
5
7C1512-25
25
120
5
7C1512-35
35
110
5
7C1512-70
70
110
5
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
June 1996 鈥?Revised October 1996
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