CY7C1482V33-250AXC Datasheet

IC型號(hào)：
CY7C1482V33-250AXC
PDF描述：
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
文件大?。?/label>
399.30KB
PDF頁數(shù)：
30頁
芯片廠家：
CYPRESS

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PRELIMINARY

CY7C1480V33

CY7C1482V33

CY7C1486V33

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined

Sync SRAM

Features

鈥?Supports bus operation up to 250 MHz

鈥?Available speed grades are 250, 200,167 MHz

鈥?Registered inputs and outputs for pipelined operation

鈥?3.3V core power supply

鈥?2.5V / 3.3V I/O operation

鈥?Fast clock-to-output times

鈥?3.0 ns (for 250-MHz device)

鈥?3.0 ns (for 200-MHz device)

鈥?3.4 ns (for 167-MHz device)

鈥?Provide high-performance 3-1-1-1 access rate

鈥?/div>

User-selectable burst counter supporting Intel

廬

Pentium

廬

interleaved or linear burst sequences

鈥?Separate processor and controller address strobes

鈥?Synchronous self-timed writes

鈥?Asynchronous output enable

鈥?Single Cycle Chip Deselect

鈥?CY7C1480V33 and CY7C1482V33 offered in

JEDEC-standard lead-free 100-pin TQFP, 165-Ball fBGA

packages. CY7C1486V33 available in 209-Ball BGA

packages

鈥?IEEE 1149.1 JTAG-Compatible Boundary Scan

鈥?鈥淶Z鈥?Sleep Mode Option

Functional Description

[1]

The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM

integrates 2,097,152 x 36/4,194,304 x 18,1,048,576 脳 72

SRAM cells with advanced synchronous peripheral circuitry

and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

Chip Enable (CE

), depth-expansion Chip Enables (CE

and

), Burst Control inputs (ADSC, ADSP, and ADV), Write

Enables (BW

, and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and the

ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates

from a +3.3V core power supply while all outputs may operate

with either a +2.5 or +3.3V supply. All inputs and outputs are

JEDEC-standard JESD8-5-compatible.

Selection Guide

250 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

Note:

1. For best-practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

200 MHz

3.0

500

120

167 MHz

3.4

450

120

Unit

3.0

500

120

Cypress Semiconductor Corporation

Document #: 38-05283 Rev. *C

鈥?/div>

3901 North First Street

鈥?/div>

San Jose

CA 95134

鈥?/div>

408-943-2600

Revised December 3, 2004

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CY7C1482V33-250AXC Datasheet

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