PRELIMINARY
CY7C1399D
256K (32K x 8) Static RAM
Features
鈥?Pin- and function-compatible with CY7C1399B
鈥?Single 3.3V power supply
鈥?Ideal for low-voltage cache memory applications
鈥?High speed
鈥?t
AA
= 8 ns
鈥?Low active power
鈥?I
CC
= 60 mA @ 10 ns
鈥?Low CMOS standby power
鈥?I
SB2
= 1.2 mA (鈥淟鈥?Version only)
鈥?Data Retention at 2.0V
鈥?Available in 28-SOJ and 28-TSOP I Pb-Free packages
Functional Description
[1]
The CY7C1399D is a high-performance 3.3V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE) and
active LOW Output Enable (OE) and tri-state drivers. The
device has an automatic power-down feature, reducing the
power consumption when deselected.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location
addressed by the address present on the address pins (A
0
through A
14
). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399D is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I Pb-Free packages.
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
INPUT BUFFER
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
CE
WE
OE
ROW DECODER
I/O
2
SENSE AMPS
32K x 8
ARRAY
I/O
3
I/O
4
I/O
5
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
10
A
11
A
12
A
13
Note:
1. For guidelines on SRAM system design, please refer to the 鈥楽ystem Design Guidelines鈥?Cypress application note, available on the internet at www.cypress.com.
A
14
Cypress Semiconductor Corporation
Document #: 38-05467 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised January 10, 2005
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