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CY7C1381CV25 Datasheet

  • CY7C1381CV25

  • Memory

  • 31頁

  • ETC

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PRELIMINARY
CY7C1381CV25
CY7C1383CV25
512K x 36 / 1M x 18 Flow-Thru SRAM
Features
Fast access times: 6.5, 7.5, 8.5 ns
Fast clock speed: 133, 117, 100 MHz
Provide high-performance 2-1-1-1 access rate
Optimal for depth expansion
2.5V
鹵
5% power supply
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
鈥?Automatic power-down available using ZZ mode or CE
deselect
鈥?Available in 100-pin TQFP, 119-ball BGA, and 165-ball
FBGA Packages
鈥?JTAG boundary scan for BGA packaging version
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chronous peripheral circuitry and a 2-bit counter for internal
burst operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs, ad-
dress-pipelining Chip Enable (CE), Burst Control Inputs
(ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc,
BWd, and BWE), and Global Write (GW).
Asynchronous inputs include the output enable (OE) and burst
mode control (MODE). The data outputs (Q), enabled by OE,
are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. BWa con-
trols DQ1鈥揇Q8 and DP1. BWb controls DQ9鈥揇Q16 and DP2.
BWc controls DQ17鈥揇Q24and DP3. BWd controls
DQ25鈥揇Q32 and DP4. BWa, BWb BWc, and BWd can be
active only with BWE being LOW. GW being LOW causes all
bytes to be written. WRITE pass-through capability allows writ-
ten data available at the output for the next ReaD cycle. This
device also incorporates pipelined enable circuit for easy
depth expansion without penalizing system performance.
All inputs and outputs of the CY7C1381CV25 and the
CY7C1383CV25 are JEDEC standard JESD8-5 compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced single
layer polysilicon, three-layer metal technology. Each memory
cell consists of six transistors.
The CY7C1381CV25 and CY7C1383CV25 SRAMs integrate
524,288x36 and 1,048,576x18SRAM cells with advanced syn-
Selection Guide
133 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
6.5
210
70
117 MHz
7.5
190
70
100 MHz
8.5
175
70
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05241 Rev. **
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3901 North First Street
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San Jose
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CA 95134 鈥?408-943-2600
Revised August 26, 2002

CY7C1381CV25相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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