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CY7C1370B-200AC Datasheet

  • CY7C1370B-200AC

  • x36 Fast Synchronous SRAM

  • 24頁(yè)

  • ETC

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PRELIMINARY
CY7C1370B
CY7C1372B
512Kx36/1Mx18 Pipelined SRAM with NoBL鈩?Architecture
Features
鈥?Zero Bus Latency, no dead cycles between write and
read cycles
鈥?Fast clock speed: 200, 166, 150, and 133 MHz
鈥?Fast access time: 3.0, 3.4, 3.8, 4.2 ns
鈥?Internally synchronized registered outputs eliminate
the need to control OE
鈥?Single 3.3V 鈥?% and +5% power supply V
DD
鈥?Separate V
DDQ
for 3.3V or 2.5V I/O
鈥?Single WE (READ/WRITE) control pin
鈥?Positive clock-edge triggered, address, data, and con-
trol signal registers for fully pipelined applications
鈥?Interleaved or linear 4-word burst capability
鈥?Individual byte write (BWSa - BWSd) control (may be
tied LOW)
鈥?CEN pin to enable clock and suspend operations
鈥?Three chip enables for simple depth expansion
鈥?JTAG boundary scan (BGA Package Only)
鈥?Available in 119-ball bump BGA and 100-pin TQFP pack-
ages
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE
1
, CE
2
, and CE
3
), cycle start input (ADV/LD),
Clock Enable (CEN), Byte Write Enables (BWSa, BWSb,
BWSc, and BWSd), and Read-Write Control (WE). BWSc and
BWSd apply to CY7C1370B only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data oc-
curs, either read or write.
A Clock Enable (CEN) pin allows operation of the
CY7C1370B/CY7C1372B to be suspended as long as neces-
sary. All synchronous inputs are ignored when CEN is HIGH
and the internal device registers will hold their previous values.
There are three chip enable pins (CE
1
, CE
2
, CE
3
) that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new mem-
ory operation can be initiated and any burst cycle in progress
is stopped. However, any pending data transfers (read or write)
will be completed. The data bus will be in high-impedance
state two cycles after the chip is deselected or a write cycle is
initiated.
The CY7C1370B and CY7C1372B have an on-chip 2-bit burst
counter. In the burst mode, the CY7C1370B and CY7C1372B
provide four cycles of data for a single address presented to
the SRAM. The order of the burst sequence is defined by the
MODE input pin. The MODE pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load
a new external address (ADV/LD=LOW) or increment the in-
ternal burst counter (ADV/LD=HIGH).
Output enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the out-
puts at any given time. ZZ may be tied to LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Functional Description
The CY7C1370B and CY7C1372B SRAMs are designed to
eliminate dead cycles when transitions from READ to WRITE
or vice versa. These SRAMs are optimized for 100 percent bus
utilization and achieve Zero Bus Latency. They integrate
524,288x36 and 1,048,576x18 SRAM cells, respectively, with
advanced synchronous peripheral circuitry and a 2-bit counter
for internal burst operation. The Synchronous Burst SRAM
family employs high-speed, low-power CMOS designs using
advanced single-layer polysilicon, three-layer metal technolo-
gy. Each memory cell consists of six transistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE
2
CE
3
WE
BWS
x
Mode
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
OUTOUT
REGISTERS
and LOGIC
D
Data-In REG.
Q
DQ
x
DP
x
CY7C1370
A
X
DQ
X
DP
X
BWS
X
.
CY7C1372
X = 19:0
X = a, b
X = a, b
X = a, b
X = 18:0
X = a, b, c, d
X = a, b, c, d
X = a, b, c, d
OE
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
June 27, 2001

CY7C1370B-200AC相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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