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CY7C1371D-100BZI Datasheet

  • CY7C1371D-100BZI

  • 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Ar...

  • 446.92KB

  • 30頁

  • CYPRESS

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PRELIMINARY
CY7C1371D
CY7C1373D
18-Mbit (512K x 36/1M x 18) Flow-Through
SRAM with NoBL鈩?Architecture
Features
鈥?/div>
No Bus Latency錚?(NoBL錚? architecture eliminates
dead cycles between write and read cycles
鈥?Can support up to 133-MHz bus operations with zero
wait states
鈥?Data is transferred on every clock
鈥?Pin-compatible and functionally equivalent to ZBT鈩?/div>
devices
鈥?Internally self-timed output buffer control to eliminate
the need to use OE
鈥?Registered inputs for flow-through operation
鈥?Byte Write capability
鈥?3.3V/2.5V I/O power supply
鈥?Fast clock-to-output times
鈥?6.5 ns (for 133-MHz device)
鈥?8.5 ns (for 100-MHz device)
鈥?Clock Enable (CEN) pin to enable clock and suspend
operation
鈥?Synchronous self-timed writes
鈥?Asynchronous Output Enable
鈥?Offered in JEDEC-standard lead-free 100 TQFP, 119-ball
BGA and 165-ball fBGA packages
鈥?Three chip enables for simple depth expansion
鈥?Automatic Power-down feature available using ZZ
mode or CE deselect
鈥?JTAG boundary scan for BGA and fBGA packages
鈥?Burst Capability鈥攍inear or interleaved burst order
鈥?Low standby power
Functional Description
[1]
The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1 Mbit x
18 Synchronous Flow-through Burst SRAM designed specifi-
cally to support unlimited true back-to-back Read/Write opera-
tions without the insertion of wait states. The CY7C1371D/
CY7C1373D is equipped with the advanced No Bus Latency
(NoBL) logic required to enable consecutive Read/Write
operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BW
X
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Selection Guide
133 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
6.5
210
70
100 MHz
8.5
175
70
Unit
ns
mA
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05556 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised November 3, 2004

CY7C1371D-100BZI相關型號PDF文件下載

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  • 英文版
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  • 英文版
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  • 英文版
    32K x 8/9 Dual-Port Static RAM
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  • 英文版
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  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
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  • 英文版
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    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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