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CY7C1321V18 Datasheet

  • CY7C1321V18

  • Memory

  • 593.88KB

  • 23頁(yè)

  • ETC

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PRELIMINARY
CY7C1317V18
CY7C1319V18
CY7C1321V18
18-Mb DDR-II SRAM
Four-word Burst Architecture
Features
鈥?18-Mb density (2M x 8, 1M x 18, 512K x 36)
鈥?Supports concurrent transactions
鈥?250-MHz clock for high bandwidth
鈥?Four-word burst for reducing address bus frequency
鈥?Double Data Rate (DDR) interfaces (data transferred at
500 MHz) @ 250 MHz
鈥?Two input clocks (K and K) for precise DDR timing
鈥?SRAM uses rising edges only
鈥?Two output clocks (C and C) accounts for clock skew
and flight time mismatches
鈥?Echo clocks (CQ and CQ) simplify data capture in high
speed systems
鈥?Synchronous internally self-timed writes
鈥?1.8V core power supply with HSTL inputs and outputs
鈥?Variable drive HSTL output buffers
鈥?Expanded HSTL output voltage (1.4V鈥揤
DD
)
鈥?13 x 15 mm 1.0-mm pitch fBGA package, 165-ball
(11 x 15 matrix)
鈥?JTAG interface
鈥?On-chip Delay Lock Loop (DLL)
Functional Description
The CY7C1317V18/CY7C1319V18/CY7C1321V18 are 1.8V
Synchronous Pipelined SRAM equipped with DDR-II (Double
Data Rate) architecture. The DDR-II consists of an SRAM core
with advanced synchronous peripheral circuitry and a two-bit
burst counter. Addresses for Read and Write are latched on
alternate rising edges of the input (K) clock. Write data is regis-
tered on the rising edges of both K and K. Read data is driven
on the rising edges of C and C if provided, or on the rising edge
of K and K if C/C are not provided. Each address location is
associated with four 8-bit words in the case of CY7C1317V18
that burst sequentially into or out of the device. The burst
counter always starts with 鈥?0鈥?internally in the case of
CY7C1317V18. On CY7C1319V18 and CY7C1321V18, the
burst counter takes in the last two significant bits of the
external address and bursts four 18-bit words in the case of
CY7C1319V18, and four 36-bit words in the case of
CY7C1321V18, sequentially into or out of the device.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs, D) are tightly matched to the two output
echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1317V18 鈥?2M x 8
CY7C1319V18 鈥?1M x 18
CY7C1321V18 鈥?512K x 36
Logic Block Diagram (CY7C1317V18)
Burst
Logic
A
(18:0)
19
LD
K
K
Write Add. Decode
Read Add. Decode
Address
Register
Write Write Write Write
Reg
Reg
Reg Reg
512K x 8 Array
512K x 8 Array
512K x 8 Array
512K x 8 Array
8
Output
Logic
Control
R/W
C
C
CQ
CQ
8
8
CLK
Gen.
Read Data Reg.
32
Control
Logic
16
Reg.
16
Reg.
Reg.
V
REF
R/W
BWS
[1:0]
DQ
[7:0]
Cypress Semiconductor Corporation
Document #: 38-05178 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised July 31, 2002

CY7C1321V18相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠(chǎng)商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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