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CY7C1373AV25-83AC Datasheet

  • CY7C1373AV25-83AC

  • x18 SRAM

  • 26頁(yè)

  • ETC

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25
PRELIMINARY
CY7C1371AV25
CY7C1373AV25
512Kx36/1Mx18 Flow-Thru SRAM with NoBL鈩?Architecture
Features
鈥?/div>
Pin compatible and functionally equivalent to ZBT錚?de-
vices
鈥?Supports 117-MHz bus operations with zero wait states
鈥?Data is transferred on every clock
鈥?Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
鈥?Registered inputs for Flow-Through operation
鈥?Byte Write capability
鈥?Common I/O architecture
鈥?Single 2.5V power supply
鈥?Fast clock-to-output times
鈥?7.5 ns (for 117-MHz device)
鈥?8.5 ns (for 100-MHz device)
鈥?9.0 ns (for 83-MHz device)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?10.0 ns (for 66-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100 TQFP & 119 BGA Packages
Burst Capability - linear or interleaved burst order
respectively designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1371AV25/CY7C1373AV25 is equipped
with the advanced No Bus Latency鈩?(NoBL錚? logic required
to enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically im-
proves the throughput of data through the SRAM, especially in
systems that require frequent Write/Read transitions.The
CY7C1371AV25/CY7C1373AV25 is pin compatible and func-
tionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 7.5 ns (117-MHz de-
vice).
Write operations are controlled by the Byte Write Selects
(BWS
a,b,c,d
for
CY7C1371AV25
and
BWS
a,b
for
CY7C1373AV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Synchronous Chip Enable (CE
1
, CE
2
, CE
3
on the TQFP, CE
1
on the BGA) and an asynchronous Output Enable (OE) pro-
vide for easy bank selection and output three-state control. In
order to avoid bus contention, the output drivers are synchro-
nously three-stated during the data portion of a write se-
quence.
Functional Description
The CY7C1371AV25 and CY7C1373AV25 are 2.5V, 512K by
36 and 1M by 18 Synchronous-Flow-Through Burst SRAMs,
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE2
CE3
WE
BWS
x
Mode
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
D
Data-In REG.
Q
AX
DQX
CY7C1371
X = 18:0
CY7C1373
X = 19:0
DQ
x
DP
x
X= a, b, c, d X = a, b
DPX X = a, b, c, d X = a, b
BWSX X = a, b, c, d X = a, b
.Introduction
OE
Selection Guide
117 MHz
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain advance information.
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
100 MHz
8.5
230
30
83 MHz
9.0
215
30
66 MHz
10.0
180
30
7.5
Com鈥檒
250
30
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
July 6, 2000

CY7C1373AV25-83AC相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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