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CY7C135-25JXC Datasheet

  • CY7C135-25JXC

  • 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with S...

  • 12頁

  • CYPRESS

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CY7C135
CY7C1342
4K x 8 Dual-Port Static RAM and 4K x 8
Dual-Port SRAM with Semaphores
Features
鈥?True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
鈥?4K x 8 organization
鈥?0.65-micron CMOS for optimum speed/power
鈥?High-speed access: 15 ns
鈥?Low operating power: I
CC
= 160 mA (max.)
鈥?Fully asynchronous operation
鈥?Automatic power-down
鈥?Semaphores included on the 7C1342 to permit software
handshaking between ports
鈥?Available in 52-pin PLCC
鈥?Pb-Free packages available
Functional Description
The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8
dual-port static RAMs. The CY7C1342 includes semaphores
that provide a means to allocate portions of the dual-port RAM
or any shared resource. Two ports are provided permitting
independent, asynchronous access for reads and writes to
any location in memory. Application areas include interpro-
cessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). The
CY7C135 is suited for those systems that do not require
on-chip arbitration or are intolerant of wait states. Therefore,
the user must be aware that simultaneous access to a location
is possible. Semaphores are offered on the CY7C1342 to
assist in arbitrating between ports. The semaphore logic is
comprised of eight shared latches. Only one side can control
the latch (semaphore) at any time. Control of a semaphore
indicates that a shared resource is in use. An automatic
power-down feature is controlled independently on each port
by a chip enable (CE) pin or SEM pin (CY7C1342 only).
The CY7C135 and CY7C1342 are available in 52-pin PLCC.
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
I/O
7L
I/O
0L
I/O
CONTROL
I/O
CONTROL
I/O
7R
I/O
0R
A
11L
A
0L
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
A
11R
A
0R
CE
L
OE
L
R/W
L
SEMAPHORE
ARBITRATION
(7C1342 only)
CE
R
OE
R
R/W
R
(7C1342 only)
SEM
R
(7C1342 only) SEM
L
Cypress Semiconductor Corporation
Document #: 38-06038 Rev. *C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised September 6, 2005

CY7C135-25JXC 產(chǎn)品屬性

  • 23

  • 集成電路 (IC)

  • 存儲器

  • -

  • RAM

  • SRAM - 雙端口，異步

  • 32K (4K x 8)

  • 25ns

  • 并聯(lián)

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 52-LCC（J 形引線）

  • 52-PLCC（19.13x19.13）

  • 管件

CY7C135-25JXC相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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