音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

CY7C1347G-166BGXI Datasheet

  • CY7C1347G-166BGXI

  • 4-Mbit (128K x 36) Pipelined Sync SRAM

  • 0頁(yè)

  • CYPRESS

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

CY7C1347G
4-Mbit (128K x 36) Pipelined Sync SRAM
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Fully registered inputs and outputs for pipelined operation
128K x 36 common IO architecture
3.3V core power supply (V
DD
)
2.5V/3.3V I/O power supply (V
DDQ
)
Fast clock-to-output times
鈥?2.6 ns (for 250-MHz device)
User-selectable burst counter supporting Intel
廬
Pentium
廬
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Offered in lead-free 100-Pin TQFP, lead-free and non-
lead-free 119-Ball BGA package and 165-Ball FBGA
package
鈥淶Z鈥?sleep mode option and stop clock option
Available in industrial and commercial temperature ranges
Functional Description
[1]
The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic. CY7C1347G IO pins can operate at
either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant
when V
DDQ
= 2.5V. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
is 2.6 ns (250 MHz device). CY7C1347G supports either the
interleaved burst sequence used by the Intel Pentium
processor or a linear burst sequence used by processors such
as the PowerPC
廬
. The burst sequence is selected through the
MODE pin. Accesses can be initiated by asserting either the
Address Strobe from Processor (ADSP) or the Address Strobe
from Controller (ADSC) at clock rise. Address advancement
through the burst sequence is controlled by the ADV input. A
2-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the four Byte Write
Select (BW
[A:D]
) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to provide proper
data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
鈥?/div>
鈥?/div>
Selection Guide
250 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.6
325
40
200 MHz
2.8
265
40
166 MHz
3.5
240
40
133 MHz
4.0
225
40
Unit
ns
mA
mA
Note
1. For best practice recommendations, refer to the Cypress application note
AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05516 Rev. *E
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised May 22, 2007
[+] Feedback

CY7C1347G-166BGXI相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

掃碼下載APP，
一鍵連接廣大的電子世界。

在線(xiàn)人工客服

買(mǎi)家服務(wù)：
賣(mài)家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線(xiàn)時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！