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CY7C1345-50AC Datasheet

  • CY7C1345-50AC

  • x36 Fast Synchronous SRAM

  • 16頁

  • ETC

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CY7C1345
128K x 36 Synchronous Flow-Through 3.3V Cache RAM
Features
鈥?Supports 117-MHz microprocessor cache systems with
zero wait states
鈥?128K by 36 common I/O
鈥?Fast clock-to-output times
鈥?7.5 ns (117-MHz version)
鈥?Two-bit wrap-around counter supporting either
interleaved or linear burst sequence
鈥?Separate processor and controller address strobes pro-
vide direct interface with the processor and external
cache controller
鈥?Synchronous self-timed write
鈥?Asynchronous output enable
鈥?Supports 3.3V & 2.5V I/O levels
鈥?JEDEC-standard pinout
鈥?100-pin TQFP packaging
鈥?ZZ 鈥渟leep鈥?mode
Functional Description
The CY7C1345 is a 3.3V, 128K by 36 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1345 allows either interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the address advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A
[16:0]
GW
BWE
BWS
3
BWS
2
BWS
1
BWS
0
CE
1
CE
2
CE
3
MODE
(A
0
,A
1
) 2
BURST Q
0
CE COUNTER
Q
1
CLR
Q
ADDRESS
CE REGISTER
D
DDQ[31:24],DP3Q
BYTEWRITE
REGISTERS
DDQ[23:16],DP2Q
BYTEWRITE
REGISTERS
D DQ[15:8],DP1 Q
BYTEWRITE
REGISTERS
D DQ[7:0],DP0 Q
BYTEWRITE
REGISTERS
D
ENABLE Q
CE REGISTER
CLK
INPUT
REGISTERS
CLK
15
17
17
15
128K X 36
MEMORY
ARRAY
36
36
OE
ZZ
SLEEP
CONTROL
DQ
[31:0]
DP
[3:0]
Selection Guide
7C1345-117
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Pentium is a registered trademark of Intel Corporation.
7C1345-100
8.0
325
10.0
7C1345-90
8.5
300
10.0
7C1345-50
11.0
250
10.0
7.5
350
10.0
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
May 8, 2000

CY7C1345-50AC相關型號PDF文件下載

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  • 英文版
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  • 英文版
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  • 英文版
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  • 英文版
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  • 英文版
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  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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