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CY7C1327F-166BGI Datasheet

  • CY7C1327F-166BGI

  • 4-Mb (256K x 18) Pipelined Sync SRAM

  • 17頁

  • CYPRESS

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CY7C1327F
4-Mb (256K x 18) Pipelined Sync SRAM
Features
鈥?Registered inputs and outputs for pipelined operation
鈥?256K 脳18 common I/O architecture
鈥?3.3V core power supply
鈥?3.3V / 2.5V I/O operation
鈥?Fast clock-to-output times
鈥?2.6 ns (for 250-MHz device)
鈥?2.6 ns (for 225-MHz device)
鈥?2.8 ns (for 200-MHz device)
鈥?3.5 ns (for 166-MHz device)
鈥?4.0 ns (for 133-MHz device)
鈥?4.5 ns (for 100-MHz device)
鈥?Provide high-performance 3-1-1-1 access rate
鈥?User-selectable burst counter supporting Intel
錚?/div>
Pentium interleaved or linear burst sequences
鈥?Separate processor and controller address strobes
鈥?Synchronous self-timed writes
鈥?Asynchronous output enable
鈥?Offered in JEDEC-standard 100-pin TQFP and 119 Ball
BGA packages.
鈥?鈥淶Z鈥?Sleep Mode Option
Functional Description
[1]
The CY7C1327F SRAM integrates 262,144 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:B]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1327F operates from a +3.3V core power supply
while all outputs also operate with a +3.3V or a +2.5V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
MODE
ADDRESS
REGISTER
2
A[1:0]
ADV
CLK
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,
DQP
B
WRITE REGISTER
DQ
B,
DQP
B
WRITE DRIVER
MEMORY
ARRAY
BW
A
BWE
GW
CE
1
CE2
CE3
OE
ENABLE
REGISTER
DQ
A,
DQP
A
WRITE REGISTER
DQ
A,
DQP
A
WRITE DRIVER
SENSE
AMPS
BW
B
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP
A
DQP
B
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
1
Note:
1. For best鈥損ractices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com
Cypress Semiconductor Corporation
Document #: 38-05216 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised December 12, 2003

CY7C1327F-166BGI相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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