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CY7C1297H-100AXI Datasheet

  • CY7C1297H-100AXI

  • 1-Mbit (64K x 18) Flow-Through Sync SRAM

  • 15頁

  • CYPRESS

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CY7C1297H
1-Mbit (64K x 18) Flow-Through Sync SRAM
Features
鈥?64K x 18 common I/O
鈥?3.3V core power supply (V
DD
)
鈥?2.5V/3.3V I/O power supply (V
DDQ
)
鈥?Fast clock-to-output times
鈥?6.5 ns (for 133-MHz version)
鈥?Provide high-performance 2-1-1-1 access rate
鈥?User-selectable burst counter supporting Intel
廬
Pentium
廬
interleaved or linear burst sequences
鈥?Separate processor and controller address strobes
鈥?Synchronous self-timed write
鈥?Asynchronous output enable
鈥?Available in JEDEC-standard lead-free 100-Pin TQFP
package
鈥?鈥淶Z鈥?Sleep Mode option
Functional Description
[1]
The CY7C1297H is a 64K x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE ), Burst
3
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:B]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1297H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1297H operates from a +3.3V core power supply
while all outputs may operate either with a +2.5V or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0,A1,A
MODE
ADDRESS
REGISTER
A[1:0]
ADV
CLK
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B
,DQP
B
WRITE REGISTER
DQ
B
,DQP
B
WRITE DRIVER
BW
B
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
BW
A
BWE
GW
DQ
A
,DQP
A
WRITE REGISTER
DQ
A
,DQP
A
WRITE DRIVER
INPUT
REGISTERS
DQs
DQP
A
DQP
B
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
ZZ
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05669 Rev. *B
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised July 6, 2006

CY7C1297H-100AXI相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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