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CY7C1277V18 Datasheet

  • CY7C1277V18

  • 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Re...

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  • CYPRESS

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CY7C1266V18
CY7C1277V18
CY7C1268V18
CY7C1270V18
36-Mbit DDR-II+ SRAM 2-Word
Burst Architecture (2.5 Cycle Read Latency)
Features
36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
300 MHz to 400 MHz clock for high bandwidth
2-Word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 800 MHz) @ 400 MHz
鈥?Read latency of 2.5 clock cycles
鈥?Two input clocks (K and K) for precise DDR timing
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
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鈥?SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high
speed systems
Data valid pin (QVLD) to indicate valid data on the output
Synchronous internally self-timed writes
Core V
DD
= 1.8V 鹵 0.1V; IO V
DDQ
= 1.4V to V
DD[1]
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
Offered in both in Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
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Functional Description
The CY7C1266V18, CY7C1277V18, CY7C1268V18, and
CY7C1270V18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II+ architecture. The DDR-II+ consists of
an SRAM core with advanced synchronous peripheral
circuitry. Addresses for read and write are latched on alternate
rising edges of the input (K) clock. Write data is registered on
the rising edges of both K and K. Read data is driven on the
rising edges of both K and K. Each address location is
associated with two 8-bit words (CY7C1266V18), 9-bit words
(CY7C1277V18), 18-bit words (CY7C1268V18), or 36-bit
words (CY7C1270V18), that burst sequentially into or out of
the device.
Asynchronous inputs include output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to
capture data separately from each individual DDR SRAM in
the system design.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1266V18 鈥?4M x 8
CY7C1277V18 鈥?4M x 9
CY7C1268V18 鈥?2M x 18
CY7C1270V18 鈥?1M x 36
Selection Guide
400 MHz
Maximum Operating Frequency
Maximum Operating Current
400
1280
375 MHz
375
1210
333 MHz
333
1080
300 MHz
300
1000
Unit
MHz
mA
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
V
DDQ
= 1.4V to V
DD
.
Cypress Semiconductor Corporation
Document Number: 001-06347 Rev. *C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised May 14, 2007
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CY7C1277V18相關(guān)型號(hào)PDF文件下載

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  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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