鈥?/div>
鈥?7.2 mW (L version)
2.0V Data Retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE options
memory expansion is provided by an active LOW Chip Enable
(CE
1
), an active HIGH Chip Enable (CE
2
), an active LOW Out-
put Enable (OE), and three-state drivers. Writing to the device
is accomplished by taking Chip Enable one (CE
1
) and Write
Enable (WE) inputs LOW and Chip Enable two (CE
2
) input
HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then
written into the location specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able one (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C109V33 is available in standard 32-pin,
400-mil-wide SOJ package. The CY7C1009V33 is available in
a 32-pin, 300-mil-wide SOJ package. The CY7C1009V33 and
CY7C109V33 are functionally equivalent in all other respects.
Functional Description
The CY7C109V33/CY7C1009V33 is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
Logic Block Diagram
Pin Configurations
SOJ
Top View
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
512 x 256 x 8
ARRAY
109V33鈥?
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
109V33鈥?
I/O
3
I/O
4
I/O
5
TSOP I
Top View
(not to scale)
CE
1
CE
2
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
109V33鈥?
Selection Guide
7C109V33-12 7C109V33-15 7C109V33-20 7C109V33-25
7C1009V33-12 7C1009V33-15 7C1009V33-20 7C1009V33-25
Maximum Access Time (ns)
12
15
20
20
Maximum Operating Current (mA)
130
120
110
110
Maximum Operating Current (mA) Low Power Version
90
80
70
70
Maximum CMOS Standby Current (mA) Standard
5
5
5
5
Maximum CMOS Standby Current (mA) Low Power Version
2
2
2
2
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
September 3, 1999
1
2
3
4
5
6
7
8
9
