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CY7C1072AV33-12BBI Datasheet

  • CY7C1072AV33-12BBI

  • 32-Mbit (1M x 32) Static RAM

  • 9頁(yè)

  • CYPRESS

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PRELIMINARY
CY7C1072AV33
32-Mbit (1M x 32) Static RAM
Features
鈥?High density 32-Mbit SRAM
鈥?High speed
鈥?t
AA
= 10 ns
鈥?Low active power
鈥?I
CC
= 450 mA
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Operating voltages of 3.3 鹵 0.3V
2.0V data retention
Automatic power-down when deselected
TTL compatible inputs and outputs
specified on the address pins (A
0
through A
19
). If Byte Enable
B (B
B
) is LOW, then data from I/O pins (I/O
8
through I/O
15
) is
written into the location specified on the address pins (A
0
through A
19
). Likewise, B
C
and B
D
correspond with the I/O
pins I/O
16
to I/O
23
and I/O
24
to I/O
31
, respectively.
Reading from the device is accomplished by enabling the chip
by taking CE
1
LOW and CE
2
HIGH while forcing the Output
Enable (OE) LOW and the Write Enable (WE) HIGH. If the first
Byte Enable (B
A
) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
Enable B (B
B
) is LOW, then data from memory will appear on
I/O
8
to I/O
15
. Similarly, B
c
and B
D
correspond to the third and
fourth bytes. See the truth table at the back of this data sheet
for a complete description of read and write modes.
The input/output pins (I/O
0
through I/O
31
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH/CE
2
LOW), the outputs are disabled (OE HIGH), the
byte selects are disabled (B
A-D
HIGH), or during a Write
operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C1072AV33 is available in a 119-ball grid array
(FBGA) package.
鈥?Available in standard 119-ball FBGA
Functional Description
The CYM1072AV33 is a 3.3V high-performance 32-Megabit
static RAM organized as 1M words by 32 bits.
Writing to the device is accomplished by enabling the chip
(CE
1
LOW and CE
2
HIGH) while forcing the Write Enable
(WE) input LOW. If Byte Enable A (B
A
) is LOW, then data from
the I/O pins (I/O
0
through I/O
7
), is written into the location
Logic Block Diagram
INPUT BUFFERS
CONTROL LOGIC
WE
CE
1
CE
2
OE
B
A
B
B
B
C
B
D
I/O
0
鈥揑/O
31
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
1024K x 32
ARRAY
COLUMN
DECODER
Selection Guide
CY7C1072AV33-10
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
10
450
100
CY7C1072AV33-12
12
400
100
Unit
ns
mA
mA
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
OUTPUT BUFFERS
SENSE AMPS
Cypress Semiconductor Corporation
Document #: 38-05635 Rev. *A
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised September 1, 2005

CY7C1072AV33-12BBI相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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