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CY7C1071AV33-10BBC Datasheet

  • CY7C1071AV33-10BBC

  • 32-Mbit (2M x 16) Static RAM

  • 10頁(yè)

  • CYPRESS

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PRELIMINARY
CY7C1071AV33
32-Mbit (2M x 16) Static RAM
Features
鈥?High density 32-Mbit SRAM
鈥?High speed
鈥?t
AA
= 10 ns
鈥?Low active power
鈥?I
CC
= 450 mA
鈥?Operating voltages of 3.3 鹵 0.3V
鈥?2.0V data retention
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Available in standard 119-ball FBGA
Low Enable (BLE) is LOW, then data from the I/O pins (I/O
0
through I/O
7
), is written into the location specified on the ad-
dress pins (A
0
through A
20
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
20
).
Reading from the device is accomplished by enabling the chip
by taking CE HIGH while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O
0
to I/O
7
. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O
8
to
I/O
15
. See the truth table at the back of this data sheet for a
complete description of Read and Write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE HIGH, and WE LOW).
The CY7C1071AV33 is available in a 119-ball grid array
(FBGA) package.
Functional Description
The CY7C1071AV33 is a 3.3V high-performance 32-Megabit
static RAM organized as a 2,097,152 words by 16 bits.
Writing to the device is accomplished by enabling the chip (CE
HIGH) while forcing the Write Enable (WE) input LOW. If Byte
Logic Block Diagram
DATA-IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
2048K 脳 16
RAM Array
SENSE AMPS
I/O
0
鈥揑/O
7
I/O
8
鈥揑/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Power-down
Circuit
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
20
CE
Cypress Semiconductor Corporation
Document #: 38-05634 Rev. *A
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised September 1, 2005

CY7C1071AV33-10BBC相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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