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Functional Description
The CY7C1061DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO
0
through IO
7
), is written
into the location specified on the address pins (A
0
through A
19
).
If Byte High Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
) is written into the location specified on the address
pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on IO
0
to IO
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO
8
to IO
15
. See the
Truth Table
on page 9
for a complete description of Read and Write modes.
The input or output pins (IO
0
through IO
15
) are placed in a high
impedance state when the device is deselected (CE
1
HIGH/CE
2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY7C1061DV33 is available in a 54-Pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-Ball VFBGA package.
High speed
鉂?/div>
t
AA
= 10 ns
Low active power
鉂?/div>
I
CC
= 175 mA at 10 ns
Low CMOS standby power
鉂?/div>
I
SB2
= 25 mA
Operating voltages of 3.3 鹵 0.3V
2.0V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Easy memory expansion with CE
1
and CE
2
features
Available in Pb-free 54-Pin TSOP II and 48-Ball VFBGA
packages
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鈻?/div>
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鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
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Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
SENSE AMPS
1M x 16
ARRAY
IO
0
鈥?IO
7
IO
8
鈥?IO
15
COLUMN
DECODER
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
BHE
WE
OE
BLE
CE
2
CE
1
Cypress Semiconductor Corporation
Document Number: 38-05476 Rev. *D
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised September 06, 2007
CY7C1061DV33-10ZSXI 產(chǎn)品屬性
CY7C1061DV33-10ZSXI相關(guān)型號PDF文件下載
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英文版
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Cypress
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英文版
32K x 8/9 Dual-Port Static RAM
Cypress
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英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
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英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
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英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
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英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Cypress
-
英文版
32K x 8/9 Dual-Port Static RAM
Cypress
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
CYPRESS
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
CYPRESS [C...
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英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
Cypress
-
英文版
16K x 16/18 Dual-Port Static RAM
Cypress
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS [C...
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS [C...
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