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CY7C1061AV33-12ZXI Datasheet

  • CY7C1061AV33-12ZXI

  • 16-Mbit (1M x 16) Static RAM

  • 642.32KB

  • 10頁

  • CYPRESS

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CY7C1061AV33
16-Mbit (1M x 16) Static RAM
Features
鈥?High speed
鈥?t
AA
= 10 ns
鈥?Low active power
鈥?990 mW (max)
鈥?Operating voltages of 3.3 鹵 0.3V
鈥?2.0V data retention
鈥?Automatic power down when deselected
鈥?TTL compatible inputs and outputs
鈥?Easy memory expansion with CE
1
and CE
2
features
鈥?Available in Pb-free and non Pb-free 54-pin TSOP II
package and non Pb-free 60-ball fine pitch ball grid array
(FBGA) package
Functional Description
The CY7C1061AV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, enable the chip (CE
1
LOW and CE
2
HIGH) while forcing the Write Enable (WE) input LOW. If Byte
Low Enable (BLE) is LOW, then data from IO pins (IO
0
through
IO
7
), is written into the location specified on the address pins
(A
0
through A
19
). If Byte High Enable (BHE) is LOW, then data
from IO pins (IO
8
through IO
15
) is written into the location
specified on the address pins (A
0
through A
19
).
To read from the device, enable the chip by taking CE
1
LOW
and CE
2
HIGH while forcing the Output Enable (OE) LOW and
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on IO
0
to IO
7
. If Byte High Enable
(BHE) is LOW, then data from memory will appear on IO
8
to
IO
15
. See
鈥淭ruth Table鈥?on page 7
for a complete description
of Read and Write modes.
The input/output pins (IO
0
through IO
15
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH/CE
2
LOW), the outputs are disabled (OE HIGH), the
BHE and BLE are disabled (BHE, BLE HIGH), or a Write
operation is in progress (CE
1
LOW, CE
2
HIGH, and WE LOW).
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
SENSE AMPS
1M x 16
ARRAY
IO
0
鈥揑O
7
IO
8
鈥揑O
15
COLUMN
DECODER
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
BHE
WE
OE
BLE
CE
2
CE
1
Cypress Semiconductor Corporation
Document #: 38-05256 Rev. *G
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised March 26, 2007
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CY7C1061AV33-12ZXI 產(chǎn)品屬性

  • 108

  • 集成電路 (IC)

  • 存儲器

  • -

  • RAM

  • SRAM - 異步

  • 16M (1M x 16)

  • 12ns

  • 并聯(lián)

  • 3 V ~ 3.6 V

  • -40°C ~ 85°C

  • 54-TSOP（0.400"，10.16mm 寬）

  • 54-TSOP II

  • 托盤

CY7C1061AV33-12ZXI相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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