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CY7C1051DV33-10BAXI Datasheet

  • CY7C1051DV33-10BAXI

  • 8-Mbit (512K x 16) Static RAM

  • 11頁

  • CYPRESS

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PRELIMINARY
CY7C1051DV33
8-Mbit (512K x 16) Static RAM
Features
鈥?High speed
鈥?t
AA
= 10 ns
鈥?Low active power
鈥?I
CC
= 110 mA @ 10 ns
鈥?Low CMOS standby power
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?I
SB2
= 20 mA
2.0V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in lead-free 48-ball FBGA and 44-pin TSOP II
packages
Functional Description
[1]
The CY7C1051DV33 is a high-performance CMOS Static
RAM organized as 512K words by 16 bits.
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW,
then data from IO pins (IO
0
鈥揑O
7
), is written into the location
specified on the address pins (A
0
鈥揂
18
). If Byte HIGH Enable
(BHE) is LOW, then data from IO pins (IO
8
鈥揑O
15
) is written into
the location specified on the address pins (A
0
鈥揂
18
).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte LOW Enable (BLE) is LOW, then data from the memory
location specified by the address pins will appear on IO
0
鈥揑O
7
.
If Byte HIGH Enable (BHE) is LOW, then data from memory
will appear on IO
8
to IO
15
. See the
鈥淭ruth Table鈥?on page 8
for
a complete description of Read and Write modes.
The input/output pins (IO
0
鈥揑O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or a Write operation (CE LOW,
and WE LOW) is in progress.
The CY7C1051DV33 is available in a 44-pin TSOP II package
with center power and ground (revolutionary) pinout, as well
as a 48-ball fine-pitch ball grid array (FBGA) package.
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
SENSE AMPS
512K 脳 16
ARRAY
IO
0
鈥揑O
7
IO
8
鈥揑O
15
COLUMN
DECODER
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
BHE
WE
CE
OE
BLE
Note
1. For guidelines on SRAM system design, please refer to the 鈥淪ystem Design Guidelines鈥?Cypress application note, available on the internet at
www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-00063 Rev. *C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised March 9, 2007
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CY7C1051DV33-10BAXI 產(chǎn)品屬性

  • CY7C1051DV33

  • 480

  • 集成電路 (IC)

  • 存儲器

  • -

  • RAM

  • SRAM - 異步

  • 8M（512K x 16）

  • 10ns

  • 并聯(lián)

  • 3 V ~ 3.6 V

  • -40°C ~ 85°C

  • 48-TFBGA

  • 48-FBGA（6x8）

  • 托盤

CY7C1051DV33-10BAXI相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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