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CY7C1049-25VC Datasheet

  • CY7C1049-25VC

  • 512K x 8 Static RAM

  • 10頁(yè)

  • CYPRESS

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049
PRELIMINARY
CY7C1049
512K x 8 Static RAM
Features
鈥?High speed
鈥?t
AA
= 15 ns
鈥?Low active power
鈥?1210 mW (max.)
鈥?Low CMOS standby power (Commercial L version)
鈥?2.75 mW (max.)
鈥?2.0V Data Retention (400
碌W
at 2.0V retention)
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Easy memory expansion with CE and OE features
is provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. Writing to the de-
vice is accomplished by taking chip enable (CE) and write en-
able (WE) inputs LOW. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
18
).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write en-
able (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049 is available in a standard 400-mil-wide 36-pin
SOJ package with center power and ground (revolutionary)
pinout.
Functional Description
The CY7C1049 is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
V
CC
GND
I/O
2
I/O3
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
GND
V
CC
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
10
NC
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
512K x 8
ARRAY
I/O
3
I/O
4
I/O
5
1049鈥?
CE
WE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
OE
1049鈥?
Selection Guide
7C1049-12
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Com鈥檒
Com鈥檒
Ind鈥檒
Military
Shaded areas contain advance information.
7C1049-15
15
220
8
0.5
9
7C1049-17
17
195
8
0.5
9
7C1049-20
20
185
8
0.5
9
10
7C1049-25
25
180
8
0.5
9
10
12
240
8
L
0.5
9
Cypress Semiconductor Corporation
Document #: 38-05063 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised August 31, 2001

CY7C1049-25VC相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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