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CY7C1046CV33-15VI Datasheet

  • CY7C1046CV33-15VI

  • 1M x 4 Static RAM

  • 9頁(yè)

  • CYPRESS

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CY7C1046CV33
1M x 4 Static RAM
Features
鈥?High speed
鈥?t
AA
= 10ns
鈥?Low active power for 10 ns speed
鈥?324 mW (max.)
鈥?2.0V data retention
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Easy memory expansion with CE and OE features
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O
0
through I/O
3
) is then written into the location
specified on the address pins (A
0
through A
19
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The four input/output pins (I/O
0
through I/O
3
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1046CV33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolu-
tionary) pinout.
Functional Description
[1]
The CY7C1046CV33 is a high-performance CMOS static
RAM organized as 1,048,576 words by 4 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
INPUT BUFFER
I/O
0
SENSE AMPS
1M x 4
ARRAY
I/O
1
I/O
2
I/O
3
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
V
CC
GND
I/O
1
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
19
A
18
A
17
A
16
A
15
OE
I/O
3
GND
V
CC
I/O
2
A
14
A
13
A
12
A
11
A
10
NC
ROW DECODER
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
-8
[2]
8
100
10
-10
10
90
10
-12
12
85
10
-15
15
80
10
Unit
ns
mA
mA
Notes:
1. For guidelines on SRAM system design, please refer to the 鈥楽ystem Design Guidelines鈥?Cypress application note, available on the internet at www.cypress.com.
2. Shaded areas contain advance information.
Cypress Semiconductor Corporation
Document #: 38-05003 Rev. *A
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised September 13, 2002

CY7C1046CV33-15VI相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
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    廠商
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  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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