CY7C1020CV33
32K x 16 Static RAM
Features
鈥?Pin- and function-compatible with CY7C1020V33
鈥?High speed
鈥?t
AA
= 10, 12, 15 ns
鈥?CMOS for optimum speed/power
鈥?Low active power
鈥?360 mW (max.)
鈥?Automatic power-down when deselected
鈥?Independent control of upper and lower bits
鈥?Available in 44-pin TSOP II
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
14
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
14
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
9
to I/O
16
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020CV33 is available in standard 44-pin TSOP
Type II packages.
Functional Description
The CY7C1020CV33 is a high-performance CMOS static
RAM organized as 32,768 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
DATA IN DRIVERS
Pin Configuration
TSOP II
Top View
NC
A
3
A
2
A
1
A
0
CE
I/O
1
I/O
2
I/O
3
I/O
4
V
CC
V
SS
I/O
5
I/O
6
I/O
7
I/O
8
WE
A
4
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
32K 脳 16
RAM Array
I/O
1
鈥揑/O
8
I/O
9
鈥揑/O
16
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
5
A
6
A
7
OE
BHE
BLE
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
V
CC
I/O
12
I/O
11
I/O
10
I/O
9
NC
A
8
A
9
A
10
A
11
NC
ROW DECODER
Selection Guide
1020CV33-10
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
10
90
5
1020CV33-12
12
85
5
1020CV33-15
15
80
5
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05133 Rev. *B
A
8
A
9
A
10
A
11
A
12
A
13
A
14
鈥?/div>
SENSE AMPS
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised August 13, 2002
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