CY7C1018CV33
128K x 8 Static RAM
Features
鈥?Pin- and function-compatible with CY7C1018BV33
鈥?High speed
鈥?t
AA
= 8, 10, 12, 15 ns
鈥?CMOS for optimum speed/power
鈥?Center power/ground pinout
鈥?Data retention at 2.0V
鈥?Automatic power-down when deselected
鈥?Easy memory expansion with CE and OE options
鈥?Available in 300-mil-wide 32-pin SOJ
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.
Functional Description
[1]
The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
0
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
16
A
15
A
14
A
13
OE
I/O
7
I/O
6
V
SS
V
CC
I/O
5
I/O
4
A
12
A
11
A
10
A
9
A
8
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
512 x 256 x 8
ARRAY
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
Selection Guide
7C1018CV33-8
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
8
95
5
7C1018CV33-10
10
90
5
7C1018CV33-12
12
85
5
7C1018CV33-15
15
80
5
Unit
ns
mA
mA
Note:
1. For guidelines on SRAM system designs, please refer to the 鈥楽ystem Design Guidelines鈥?Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05131 Rev. *C
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised September 13, 2002
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