鈥?/div>
鈥?I
SB2
= 10 mA
Data Retention at 2.0 V
Automatic power-down when deselected
Independent control of upper and lower bits
Easy memory expansion with CE and OE features
Available in Lead-Free 44-pin TSOP II, and 48-ball VFBGA
Functional Description
The CY7C1011DV33 is a high-performance CMOS Static
RAM organized as 128K words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011DV33 is available in standard Lead-Free
44-pin TSOP II with center power and ground pinout, as well
as 48-ball fine-pitch ball grid array (VFBGA) packages
.
Logic Block Diagram
INPUT BUFFER
Pin Configuration
TSOP II
Top View
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
16
A
15
A
14
A
13
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
0
鈥揑/O
7
I/O
8
鈥揑/O
15
128K X 16
COLUMN
DECODER
BHE
WE
CE
OE
BLE
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
NC
ROW DECODER
Note
1. For guidelines on SRAM system design, please refer to the 鈥淪ystem Design Guidelines鈥?Cypress application note, available on the internet at www.cypress.com
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
SENSE AMPS
Cypress Semiconductor Corporation
Document #: 38-05609 Rev. *C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised July 14, 2006
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