鈻?/div>
Functional Description
The CY7C1011CV33 is a high performance CMOS static RAM
organized as 131,072 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
), is written into the location
specified on the address pins (A
0
through A
16
). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO
8
through IO
15
)
is written into the location specified on the address pins (A
0
through A
16
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO
0
to IO
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO
8
to IO
15
. For more information, see the
鈥淭ruth
Table鈥?/span>
on page 9 for a complete description of Read and Write
modes.
The input and output pins (IO
0
through IO
15
) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System Guidelines.
Temperature ranges
鉂?/div>
Commercial: 0擄C to 70擄C
鉂?/div>
Industrial: 鈥?0擄C to 85擄C
鉂?/div>
Automotive-A: 鈥?0擄C to 85擄C
Pin and function compatible with CY7C1011BV33
High speed
鉂?/div>
t
AA
= 10 ns
Low active power
鉂?/div>
360 mW (max)
Data Retention at 2.0
Automatic power down when deselected
Independent control of upper and lower bits
Easy memory expansion with CE and OE features
Available in Pb-free and non Pb-free 44-pin TSOP II, 44-pin
TQFP and 48-Ball VFBGA packages
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
128K x 16
RAM Array
SENSE AMPS
IO
0
鈥揑O
7
IO
8
鈥揑O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
10
A
11
A
12
A
14
A
15
A
13
A
16
A
9
Cypress Semiconductor Corporation
Document Number: 38-05232 Rev. *F
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised January 04, 2008
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