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CY7C1001-20VC Datasheet

  • CY7C1001-20VC

  • 256K x 4 Static RAM with Separate I/O

  • 10頁

  • CYPRESS

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PRELIMINARY
CY7C1001
CY7C1002
Features
D
D
D
D
D
D
D
D
High speed
t
AA
= 12 ns
Transparent write (7C1001)
CMOS for optimum speed/power
Low active power
910 mW
Low standby power
275 mW
2.0V data retention (optional)
100
碌
W
Automatic power down when
deselected
TTL compatible inputs and outputs
The CY7C1001 and CY7C1002 are high
performance CMOS static RAMs orga
nized as 262,144 x 4 bits with separate I/O.
Easy memory expansion is provided by ac
tive LOW chip enable (CE) and three
state drivers. Both devices have an auto
matic power down feature, reducing the
power consumption by more than 65%
when deselected.
Writing to the device is accomplished by
taking both chip enable (CE) and write en
able (WE) inputs LOW. Data on the four
input pins (I
0
through I
3
) is written into the
memory location specified on the address
pins (A
0
through A
17
).
Reading the device is accomplished by tak
ing chip enable (CE) LOW while write en
I
0
I
1
Functional Description
256K x 4 Static RAM
with Separate I/O
able (WE) remains HIGH. Under these
conditions, the contents of the memory lo
cation specified on the address pins will ap
pear on the four data output pins (O
0
through O
3
).
The data output pins on the CY7C1001
and the CY7C1002 are placed in a high
impedance state when the device is dese
lected (CE HIGH). The CY7C1002's out
puts are also placed in a high impedance
state during a write operation (CE and WE
LOW). In a write operation on the
CY7C1001, the output pins will carry the
same data as the inputs after a specified
delay.
The CY7C1001 and CY7C1002 are avail
able in standard 300 mil wide DIPs and
SOJs.
DIP/SOJ
Top View
Logic Block Diagram
Pin Configuration
I
2
I
3
NC
A
16
A
17
A
0
A
1
A
2
A
10
A
11
A
12
A
13
A
14
A
9
I
3
I
2
CE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
7C1001
7C1002
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
A
3
A
4
A
5
A
6
A
7
A
8
NC
I
0
I
1
O
0
O
1
O
2
O
3
WE
C1001-2
INPUT BUFFER
A
2
A
3
A
4
A
5
A
6
A
7
A
8
SENSE AMPS
A
1
ROW DECODER
A
0
O
0
O
1
512 x 512 x 4
ARRAY
O
2
O
3
COLUMN
DECODER
POWER
DOWN
A
12
A
13
A
14
A
15
A
16
A
17
A
10
A
11
A
9
CE
7C1002 ONLY
WE
7C1001 ONLY
C1001-1
Selection Guide
7C1001-12
7C1001-15
7C1002-15
7C1001-20
7C1002-20
7C1001-25
7C1002-25
Maximum Access Time (ns)
Maximum Operating Current
7C1002-12
Commercial
Military
Maximum Standby Current (mA) Commercial
Military
Cypress Semiconductor Corporation
12
165
50
15
155
165
40
40
20
140
150
30
30
25
130
140
30
30
D
3901 North First Street
1
D
San Jose
D
CA 95134
D
408-943-2600
November 1991 - Revised April 1995

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