鈥?/div>
鈥?Supported in Flow-Through and Pipelined modes
Counter Address Read Back via I/O lines
Single Chip Enable
Automatic power-down
Commercial and Industrial Temperature Ranges
Compact package
鈥?144-Pin TQFP (20 x 20 x 1.4 mm)
鈥?172-Ball BGA (1.0-mm pitch) (15 x 15 x 0.51 mm)
Logic Block Diagram
R/W
L
OE
L
B
0
鈥揃
3
CE
L
FT/Pipe
L
Left
Port
Control
Logic
Right
Port
Control
Logic
R/W
R
OE
R
CE
R
FT/Pipe
R
BE
9
9
9
I/O
0L
鈥揑/O
8L
9
I/O
9L
鈥揑/O
17L
9
I/O
Control
I/O
Control
9
9
Bus
Match
9/18/36
I/O
R
I/O
18L
鈥揑/O
26L
9
I/O
27L
鈥揑/O
35L
A
0
鈥揂
13/14L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
[1]
BM
SIZE
14/15
14/15
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
A
0
鈥揂
13/14R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
[1]
Note:
1. A
0
鈥揂
13
for 16K; A
0
鈥揂
14
for 32K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
鈥?3901 North First Street 鈥?San Jose 鈥?CA 95134 鈥?408-943-2600
Document #: 38-06054 Rev. **
Revised September 7, 2001