鈥?/div>
Standby= 10
碌A
(typical)
鈥?Fully synchronous interface for easier operation
鈥?Burst counters increment addresses internally
鈥?Shorten cycle times
鈥?Minimize bus noise
鈥?Supported in Flow-Through and Pipelined modes
鈥?Dual Chip Enables for easy depth expansion
鈥?Automatic power-down
鈥?Commercial and Industrial temperature ranges
鈥?Available in 100-pin TQFP
鈥?Pb-Free packages available
Logic Block Diagram
R/W
L
OE
L
R/W
R
OE
R
CE
0L
CE
1L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
FT/Pipe
L
I/O
0L
鈥揑/O
7/8L
[2]
0/1
1
0
0
1
0/1
FT/Pipe
R
I/O
0R
鈥揑/O
7/8R
[2]
8/9
8/9
I/O
Control
15/16/17
I/O
Control
15/16/17
[3]
A
0
鈥揂
14/15/16L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
A
0
鈥揂
14/15/16R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
[3]
Notes:
1. See page 6 for Load Conditions.
2. I/O
0
鈥揑/O
7
for x8 devices, I/O
0
鈥揑/O
8
for x9 devices.
3. A
0
鈥揂
14
for 32K, A
0
鈥揂
15
for 64K, and A
0
鈥揂
16
for 128K devices.
Cypress Semiconductor Corporation
Document #: 38-06043 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised May 18, 2005
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