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CY7C027-12AC Datasheet

  • CY7C027-12AC

  • 32K/64K x 16/18 Dual-Port Static RAM

  • 19頁

  • CYPRESS

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25/0251
CY7C027/028
CY7C037/038
32K/64K x 16/18
Dual-Port Static RAM
Features
鈥?True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
鈥?32K x 16 organization (CY7C027)
鈥?64K x 16 organization (CY7C028)
鈥?32K x 18 organization (CY7C037)
鈥?64K x 18 organization (CY7C038)
鈥?0.35-micron CMOS for optimum speed/power
鈥?High-speed access: 12
[1]
/15/20 ns
鈥?Low operating power
鈥?/div>
Active: I
CC
= 180 mA (typical)
鈥?Standby: I
SB3
= 0.05 mA (typical)
鈥?Fully asynchronous operation
鈥?Automatic power-down
鈥?Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
鈥?On-chip arbitration logic
鈥?Semaphores included to permit software handshaking
between ports
鈥?INT flags for port-to-port communication
鈥?Separate upper-byte and lower-byte control
鈥?Dual Chip Enables
鈥?Pin select for Master or Slave
鈥?Commercial and industrial temperature ranges
鈥?Available in 100-pin TQFP
鈥?Pin-compatible and functionally equivalent to IDT7027
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
0L
CE
1L
LB
L
OE
L
CE
L
CE
R
CE
0R
CE
1R
LB
R
OE
R
I/O
8/9L
鈥揑/O
15/17L
[3]
[2]
8/9
8/9
8/9
[2]
I/O
0L
鈥揑/O
7/8L
I/O
Control
I/O
Control
8/9
I/O
8/9L
鈥揑/O
15/17R
[3]
I/O
0L
鈥揑/O
7/8R
A
0L
鈥揂
14/15L
[4]
15/16
Address
Decode
15/16
True Dual-Ported
RAM Array
Address
Decode
15/16
15/16
A
0R
鈥揂
14/15R
[4]
[4]
A
0L
鈥揂
14/15L
CE
L
OE
L
R/W
L
SEM
L
BUSY
L
INT
L
UB
L
LB
L
[5]
Interrupt
Semaphore
Arbitration
A
0R
鈥揂
14/15R
CE
R
OE
R
R/W
R
SEM
R
[5]
[4]
M/S
4.
5.
BUSY
R
INT
R
UB
R
LB
R
A
0
鈥揂
14
for 32K; A
0
鈥揂
15
for 64K devices.
BUSY is an output in master mode and an input in slave mode.
Notes:
1. See page 6 for Load Conditions.
2. I/O
8
鈥揑/O
15
for x16 devices; I/O
9
鈥揑/O
17
for x18 devices.
3. I/O
0
鈥揑/O
7
for x16 devices; I/O
0
鈥揑/O
8
for x18 devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
鈥?3901 North First Street 鈥?San Jose 鈥?CA 95134 鈥?408-943-2600
Document #: 38-06042 Rev. *A
Revised December 27, 2002

CY7C027-12AC相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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