鈥?/div>
Active: I
CC
= 180 mA (typical)
鈥?Standby: I
SB3
= 0.05 mA (typical)
鈥?Fully asynchronous operation
鈥?Automatic power-down
鈥?Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
鈥?On-chip arbitration logic
鈥?Semaphores included to permit software handshaking
between ports
鈥?INT flags for port-to-port communication
鈥?Separate upper-byte and lower-byte control
鈥?Pin select for Master or Slave
鈥?Commercial and Industrial temperature ranges
鈥?Available in 100-Pin TQFP
鈥?Pin-compatible and functionally equivalent to IDT70261
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
L
LB
L
OE
L
CE
R
LB
R
OE
R
I/O
8/9L
鈥揑/O
15/17L
[3]
[2]
8/9
8/9
8/9
[2]
I/O
0L
鈥揑/O
7/8L
I/O
Control
I/O
Control
8/9
I/O
8/9L
鈥揑/O
15/17R
[3]
I/O
0L
鈥揑/O
7/8R
14
A
0L
鈥揂
13L
Address
Decode
14
True Dual-Ported
RAM Array
Address
Decode
14
14
A
0R
鈥揂
13R
A
0L
鈥揂
13L
CE
L
OE
L
R/W
L
SEM
L
[4]
Interrupt
Semaphore
Arbitration
[4]
A
0R
鈥揂
13R
CE
R
OE
R
R/W
R
SEM
R
BUSY
R
INT
R
UB
R
LB
R
BUSY
L
INT
L
UB
L
LB
L
Notes:
1. See page 6 for Load Conditions.
2. I/O
8
鈥揑/O
15
for x16 devices; I/O
9
鈥揑/O
17
for x18 devices.
3. I/O
0
鈥揑/O
7
for x16 devices; I/O
0
鈥揑/O
8
for x18 devices.
4. BUSY is an output in master mode and an input in slave mode.
M/S
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
鈥?3901 North First Street 鈥?San Jose 鈥?CA 95134 鈥?408-943-2600
Document #: 38-06046 Rev. *A
Revised December 27, 2002