鈥?/div>
Active: I
CC
= 115 mA (typical)
鈥?Standby: I
SB3
= 10
碌A(chǔ)
(typical)
鈥?Fully asynchronous operation
鈥?Automatic power-down
鈥?Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
鈥?On-chip arbitration logic
鈥?Semaphores included to permit software handshaking
between ports
鈥?INT flag for port-to-port communication
鈥?Dual Chip Enables
鈥?Pin select for Master or Slave
鈥?Commercial and Industrial Temperature Ranges
鈥?Available in 100-pin TQFP
Logic Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
CE
L
CE
R
R/W
R
CE
0R
CE
1R
OE
R
[1]
8/9
8/9
[1]
I/O
0L
鈥揑/O
7/8L
I/O
Control
I/O
Control
I/O
0R
鈥揑/O
7/8R
A
0L
鈥揂
15/16L
[2]
16/17
Address
Decode
16/17
True Dual-Ported
RAM Array
Address
Decode
16/17
16/17
A
0R
鈥揂
15/16R
[2]
[2]
A
0L
鈥揂
15/16L
CE
L
OE
L
R/W
L
SEM
L
[3]
Interrupt
Semaphore
Arbitration
A
0R
鈥揂
15/16R
CE
R
OE
R
R/W
R
SEM
R
[3]
[2]
BUSY
L
INT
L
M/S
BUSY
R
INT
R
Notes:
1. I/O
0
鈥揑/O
7
for x8 devices; I/O
0
鈥揑/O
8
for x9 devices.
2. A
0
鈥揂
15
for 64K devices; A
0
鈥揂
16
for 128K.
3. BUSY is an output in master mode and an input in slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
鈥?3901 North First Street 鈥?San Jose 鈥?CA 95134 鈥?408-943-2600
Document #: 38-06044 Rev. *B
Revised December 27, 2002