CY7C008/009
CY7C018/01964K/128K x 8/9 Dual-Port Static RAM
CY7C008/009
CY7C018/019
64K/128K x 8/9 Dual-Port Static RAM
Features
鈥?True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
鈥?64K x 8 organization (CY7C008)
鈥?128K x 8 organization (CY7C009)
鈥?64K x 9 organization (CY7C018)
鈥?128K x 9 organization (CY7C019)
鈥?0.35-micron CMOS for optimum speed/power
鈥?High-speed access: 12
[1]
/15/20 ns
鈥?Low operating power
鈥?/div>
Active: I
CC
= 180 mA (typical)
鈥?Standby: I
SB3
= 0.05 mA (typical)
鈥?Fully asynchronous operation
鈥?Automatic power-down
鈥?Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
鈥?On-chip arbitration logic
鈥?Semaphores included to permit software handshaking
between ports
鈥?INT flags for port-to-port communication
鈥?Dual Chip Enables
鈥?Pin select for Master or Slave
鈥?Commercial and Industrial temperature ranges
鈥?Available in 100-pin TQFP
Logic Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
CE
L
CE
R
R/W
R
CE
0R
CE
1R
OE
R
[2]
8/9
8/9
[2]
I/O
0L
鈥揑/O
7/8L
I/O
Control
I/O
Control
I/O
0R
鈥揑/O
7/8R
A
0L
鈥揂
15/16L
[3]
16/17
Address
Decode
16/17
True Dual-Ported
RAM Array
Address
Decode
16/17
16/17
A
0R
鈥揂
15/16R
[3]
[3]
[3]
A
0L
鈥揂
15/16L
CE
L
OE
L
R/W
L
SEM
L
[4]
Interrupt
Semaphore
Arbitration
A
0R
鈥揂
15/16R
CE
R
OE
R
R/W
R
SEM
R
[4]
BUSY
L
INT
L
M/S
Notes:
1.
2.
3.
4.
See page 6 for Load Conditions.
I/O
0
鈥揑/O
7
for x8 devices; I/O
0
鈥揑/O
8
for x9 devices.
A
0
鈥揂
15
for 64K devices; A
0
鈥揂
16
for 128K.
BUSY is an output in master mode and an input in slave mode.
BUSY
R
INT
R
Cypress Semiconductor Corporation
Document #: 38-06041 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised June 22, 2004
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