CY7C007 A
CY7C017 A32K/16 K x 8, 32 K x 9
Dual-Po rt Static RAM
1
CY7C006A, CY7C007A
CY7C016A, CY7C017A
32K/16K x8, 32K/16K x9
Dual-Port Static RAM
Features
鈥?True dual-ported memory cells which allow simulta-
neous access of the same memory location
鈥?16K x 8 organization (CY7C006A)
鈥?32K x 8 organization (CY7C007A)
鈥?16K x 9 organization (CY7C016A)
鈥?32K x 9 organization (CY7C017A)
鈥?0.35-micron CMOS for optimum speed/power
鈥?High-speed access: 12
[1]
/15/20 ns
鈥?Low operating power
鈥?Active: I
CC
= 180 mA (typical)
鈥?Standby: I
SB3
= 0.05 mA (typical)
鈥?Fully asynchronous operation
鈥?Automatic power-down
鈥?Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
鈥?On-chip arbitration logic
鈥?Semaphores included to permit software handshaking
between ports
鈥?INT flags for port-to-port communication
鈥?Pin select for Master or Slave
鈥?Commercial temperature range
鈥?Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
鈥?Pin-compatible and functionally equivalent to IDT7006
and IDT7007
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
[2]
8/9
8/9
[2]
I/O
0L
鈥揑/O
7/8L
I/O
Control
I/O
Control
I/O
0R
鈥揑/O
7/8R
A
0L
鈥揂
13/14L
[4]
14/15
Address
Decode
14/15
True Dual-Ported
RAM Array
Address
Decode
14/15
14/15
A
0R
鈥揂
13/14R
[4]
[4]
A
0L
鈥揂
13/14L
CE
L
OE
L
R/W
L
SEM
L
BUSY
L
INT
L
Interrupt
Semaphore
Arbitration
[3]
A
0R
鈥揂
13/14R
CE
R
OE
R
R/W
R
SEM
R
BUSY
R
INT
R
[4]
[3]
M/S
Notes:
1. See page 7 for Load Conditions.
2. I/O
0
鈥揑/O
7
for x8 devices; I/O
0
鈥揑/O
8
for x9 devices.
3. BUSY is an output in master mode and an input in slave mode.
4. A
0
鈥揂
13
for 16K; A
0
鈥揂
14
for 32K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
January 10, 2001
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