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CY7B9950AC Datasheet

  • CY7B9950AC

  • 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer

  • 9頁

  • CYPRESS

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RoboClock
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CY7B9950
2.5/3.3V, 200-MHz High-Speed Multi-Phase
PLL Clock Buffer
Features
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2.5V or 3.3V operation
Split output bank power supplies
Output frequency range: 6 MHz to 200 MHz
Output-output skew < 100 ps
Cycle-cycle jitter < 100 ps
鹵 2% max output duty cycle
Selectable output drive strength
Selectable positive or negative edge synchronization
Eight LVTTL outputs driving 50鈩?terminated lines
LVCMOS/LVTTL over-voltage-tolerant reference input
Phase adjustments in 625-/1250-ps steps up to +7.5 ns
2x, 4x multiply and (1/2)x, (1/4)x divide ratios
Spread-Spectrum-compatible
Industrial temp. range: 鈥?0擄C to +85擄C
32-pin TQFP package
Description
The CY7B9950 RoboClock
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is a low-voltage, low-power,
eight-output, 200-MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance computer and communication systems.
The user can program the phase of the output banks through
nF[0:1] pins. The adjustable phase feature allows the user to
skew the outputs to lead or lag the reference clock. Any one
of the outputs can be connected to feedback input to achieve
different reference frequency multiplication and divide ratios
and zero input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin
controls the synchronization of the output signals to either the
rising or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from 鹵 12 mA to
鹵 24 mA(3.3V).
Block Diagram
TEST PE/HD FS
VDDQ1
Pin Configuration
VDD
REF
3F0
32
31
30
29
28
27
26
3F1
3
1F1:0
3
Phase
Select
1Q0
1Q1
4F0
4F1
PE/HD
VDDQ4
4Q1
4Q0
VSS
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
9
25
24
23
22
1F1
1F0
sOE#
VDDQ1
1Q0
1Q1
VSS
VSS
21
20
19
18
17
2Q0
FB
PLL
CY7B9950
3
2F1:0
3
Phase
Select
2Q0
2Q1
VDDQ3
3Q1
VSS
FS
3
3F1:0
3
Phase
Select
and /K
3Q1
VDDQ3
3
4F1:0
3
Phase
Select
and /M
4Q0
4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation
Document #: 38-07338 Rev. *B
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3901 North First Street
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San Jose
,
CA 95134
VSS
3Q0
VDD
3Q0
2Q1
FB
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408-943-2600
Revised March 4, 2003
2F1
REF
2F0
3
3
3
TEST

CY7B9950AC相關(guān)型號PDF文件下載

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    CYPRESS
  • 英文版
    4K x8/9 Dual-Port Static RAM with Sem, Int, Busy
    CYPRESS [C...

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