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CY7B9945V-2AXI Datasheet

  • CY7B9945V-2AXI

  • High Speed Multi-phase PLL Clock Buffer

  • 11頁

  • CYPRESS

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PRELIMINARY
RoboClock
廬
CY7B9945V
High Speed Multi-phase PLL Clock Buffer
Features
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Functional Description
The CY7B9945V high speed multi-phase PLL clock buffer offers
user selectable control over system clock functions. This multiple
output clock driver provides the system integrator with functions
necessary to optimize the timing of high performance computer
and communication systems.
The device features a guaranteed maximum TTB window speci-
fying all occurrences of output clocks. This includes the input
reference clock across variations in output frequency, supply
voltage, operating temperature, input edge rate, and process.
Ten configurable outputs each drive terminated transmission
lines with impedances as low as 50W while delivering minimal
and specified output skews at LVTTL levels. The outputs are
arranged in two banks of four and six outputs. These banks
enable a divide function of 1 to 12, with phase adjustments in 625
ps鈥?300 ps increments up to 鹵10.4 ns. The dedicated feedback
output enables divide-by functionality from 1 to 12 and limited
phase adjustments. However, if needed, any one of the ten
outputs can be connected to the feedback input as well as driving
other inputs.
Selectable reference input is a fault tolerant feature that enables
smooth change over to a secondary clock source when the
primary clock source is not in operation. The reference inputs
and feedback inputs are configurable to accommodate both
LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
500 ps max Total Timing Budget鈩?(TTB鈩? window
24鈥?00 MHz input and output operation
Low output-output skew < 200 ps
10 + 1 LVTTL outputs driving 50W terminated lines
Dedicated feedback output
Phase adjustments in 625/1300 ps steps up to +10.4 ns
3.3V LVTTL/LVPECL, fault tolerant, and hot insertable
reference inputs
Multiply or divide ratios of 1鈥?, 8, 10, and 12
Individual output bank disable
Output high impedance option for testing purposes
Integrated phase locked loop (PLL) with lock indicator
Low cycle-cycle jitter (<100 ps peak-peak)
3.3V operation
Industrial temperature range: 鈥?0擄C to +85擄C
52-pin 1.4 mm TQFP package
Logic Block Diagram
FS
3
REFA+
REFA-
LO C K
REFB+
REFB-
REFSEL
FBK
MODE
FBF0
FBDS0
FBDS1
PLL
3
3
3
D iv id e
and
Phase
S e le c t
QF
1F0
1F1
1D S0
1D S1
1F2
1F3
3
3
3
3
3
3
D IS 1
1Q 0
1Q 1
D iv id e
and
Phase
S e le c t
1Q 2
1Q 3
2Q 0
2F0
2F1
2D S 0
2D S1
3
3
3
3
2Q 1
D iv id e
and
Phase
S e le c t
2Q 2
2Q 3
2Q 4
2Q 5
D IS 2
Cypress Semiconductor Corporation
Document Number: 38-07336 Rev. *F
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198 Champion Court
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San Jose
,
CA 95134-1709
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408-943-2600
Revised June 21, 2007
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CY7B9945V-2AXI 產(chǎn)品屬性

  • CY7B9945V

  • 160

  • 集成電路 (IC)

  • 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器

  • RoboClock™

  • 時鐘緩沖器，扇出配送

  • 是

  • LVPECL，LVTTL

  • LVTTL

  • 1

  • 4:10

  • 是/無

  • 200MHz

  • 是/是

  • 2.97 V ~ 3.63 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 52-LQFP

  • 52-TQFP（10x10）

  • 托盤

  • 428-2247CY7B9945V-2AXI-ND

CY7B9945V-2AXI相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
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  • 英文版
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    ETC
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  • 英文版
    4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM...
    CYPRESS [C...
  • 英文版
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    4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM...
    CYPRESS [C...
  • 英文版
    4K x8/9 Dual-Port Static RAM with Sem, Int, Busy
    CYPRESS
  • 英文版
    4K x8/9 Dual-Port Static RAM with Sem, Int, Busy
    CYPRESS [C...
  • 英文版
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    CYPRESS
  • 英文版
    4K x8/9 Dual-Port Static RAM with Sem, Int, Busy
    CYPRESS [C...

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