鈻?/div>
Single 3.3V 鹵 10% supply
44-pin TQFP package
Functional Description
The CY7B9930V and CY7B9940V High-Speed Multifrequency
PLL Clock Buffers offer user-selectable control over system
clock functions. This multiple output clock driver provides the
system integrator with functions necessary to optimize the timing
of high performance computer or communication systems.
Ten configurable outputs can each drive terminated transmission
lines with impedances as low as 50惟 while delivering minimal and
specified output skews at LVTTL levels. The outputs are arranged
in three banks. The FB feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12. Any one of
these ten outputs can be connected to the feedback input as well
as driving other inputs.
Selectable reference input is a fault tolerance feature that allows
smooth change over to secondary clock source, when the
primary clock source is not in operation. The reference inputs are
configurable to accommodate both LVTTL or differential
(LVPECL) inputs. The completely integrated PLL reduces jitter
and simplifies board layout.
Block Diagram
FBKA
Phase
Freq.
Detector
VCO
Control Logic
Divide
Generator
LOCK
Filter
REFA+
REFA鈥?/div>
REFB+
REFB鈥?/div>
REFSEL
FS
Output_Mode
3
3
Feedback Bank
FBDS0
FBDS1
3
3
Divide
Matrix
QFA0
QFA1
2QA0
2QA1
Bank 2
DIS2
2QB0
2QB1
1QA0
1QA1
Bank 1
DIS1
1QB0
1QB1
Cypress Semiconductor Corporation
Document Number: 38-07271 Rev. *C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised August 8, 2007
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