RoboClockII鈩?Junior
CY7B9930V
CY7B9940V
High-Speed Multi-Frequency PLL Clock Buffer
Features
鈥?12鈥?00 MHz (CY7B9930V), or 24鈥?00 MHz (CY7B9940V)
input/output operation
鈥?Matched pair output skew < 200 ps
鈥?Zero input-to-output delay
鈥?10 LVTTL 50% duty-cycle outputs capable of driving
50蠅 terminated lines
鈥?Commercial temp. range with eight outputs at 200 MHz
鈥?Industrial temp. range with eight outputs at 200 MHz
鈥?3.3V LVTTL/LV differential (LVPECL), fault-tolerant and
hot insertable reference inputs
鈥?Multiply ratios of (1鈥?, 8, 10, 12)
鈥?Operation up to 12x input frequency
鈥?Individual output bank disable for aggressive power
management and EMI reduction
鈥?Output high-impedance option for testing purposes
鈥?Fully integrated PLL with lock indicator
鈥?Low cycle-to-cycle jitter (<100 ps peak-peak)
鈥?Single 3.3V 鹵 10% supply
鈥?44-pin TQFP package
Functional Description
The CY7B9930V and CY7B9940V High-Speed Multi-
Frequency PLL Clock Buffers offer user-selectable control
over system clock functions. This multiple-output clock driver
provides the system integrator with functions necessary to
optimize the timing of high-performance computer or commu-
nication systems.
Ten configurable outputs can each drive terminated trans-
mission lines with impedances as low as 50鈩?while delivering
minimal and specified output skews at LVTTL levels. The outputs
are arranged in three banks. The FB feedback bank consists
of two outputs, which allows divide-by functionality from 1 to
12. Any one of these ten outputs can be connected to the
feedback input as well as driving other inputs.
Selectable reference input is a fault tolerance feature that
allows smooth change over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs are configurable to accommodate both LVTTL or Differ-
ential (LVPECL) inputs. The completely integrated PLL
reduces jitter and simplifies board layout.
Functional Block Diagram
FBKA
Phase
Freq.
Detector
VCO
Control Logic
Divide
Generator
LOCK
Filter
Pin Configuration
44-Pin TQFP
FBDS1
FBDS0
VCCQ
VCCN
LOCK
FBKA
QFA0
QFA1
GND
GND
GND
REFA+
REFA鈥?/div>
REFB+
REFB鈥?/div>
REFSEL
FS
Output_Mode
3
3
GND
2QB1
1
2
3
4
5
6
7
8
9
10
11
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
VCCQ
REFA+
REFA 鈥?/div>
REFSEL
REFB鈥?/div>
REFB+
FS
GND
VCCQ
DIS2
DIS1
Feedback Bank
FBDS0
FBDS1
3
3
Divide
Matrix
QFA0
QFA1
VCCN
2QB0
GND
2QA0
2QA1
GND
2QA1
VCCN
2QA0
GND
GND
CY7B9930V/40V
29
28
27
26
25
24
23
Bank 2
DIS2
2QB0
2QB1
1QA0
1QA1
12
13 14 15 16 17 18 19 20 21 22
Bank 1
DIS1
1QB0
1QB1
1QA0
1QA1
GND
GND
GND
VCCN
1QB0
1QB1
Output_Mode
VCCN
GND
Cypress Semiconductor Corporation
Document #: 38-07271 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised July 25, 2002
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