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CY7B991-7LMB[27] Datasheet

  • CY7B991-7LMB[27]

  • Programmable Skew Clock Buffer

  • 19頁

  • CYPRESS

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CY7B991
CY7B992
Programmable Skew Clock Buffer
Features
鈻?/div>
鈻?/div>
鈻?/div>
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buffers
(PSCB) offer user selectable control over system clock functions.
These multiple output clock drivers provide the system integrator
with functions necessary to optimize the timing of high perfor-
mance computer systems. Each of the eight individual drivers,
arranged in four pairs of user controllable outputs, can drive
terminated transmission lines with impedances as low as 50惟.
They can deliver minimal and specified output skews and full
swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output is hardwired to one of the nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined
by the operating frequency with outputs that skew up to 鹵6 time
units from their nominal 鈥渮ero鈥?skew position. The completely
integrated PLL allows cancellation of external load and trans-
mission line delay effects. When this 鈥渮ero delay鈥?capability of the
PSCB is combined with the selectable output skew functions,
you can create output-to-output delays of up to 鹵12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that are multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty, allowing maximum system clock speed and
flexibility.
All output pair skew <100 ps typical (250 maximum)
3.75 to 80 MHz output operation
User selectable output functions
鉂?/div>
Selectable skew to 18 ns
鉂?/div>
Inverted and non-inverted
鉂?/div>
Operation at 1鈦? and 1鈦? input frequency
鉂?/div>
Operation at 2x and 4x input frequency (input as low as 3.75
MHz)
Zero input to output delay
50% duty cycle outputs
Outputs drive 50惟 terminated lines
Low operating current
32-pin PLCC/LCC package
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
鈻?/div>
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鈻?/div>
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Logic Block Diagram
TEST
FB
REF
FS
4F0
4F1
4Q0
SELECT
INPUTS
(THREE
LEVEL)
4Q1
SKEW
3Q0
3Q1
2Q0
MATRIX
2Q1
1Q0
1Q1
PHASE
FREQ
DET
VCO AND
TIME UNIT
GENERATOR
FILTER
3F0
3F1
SELECT
2F0
2F1
1F0
1F1
Cypress Semiconductor Corporation
Document Number: 38-07138 Rev. *B
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised June 22, 2007

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