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CY7B9910-2SCT Datasheet

  • CY7B9910-2SCT

  • Low Skew Clock Buffer

  • 11頁

  • CYPRESS

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CY7B9910
CY7B9920
Low Skew Clock Buffer
Features
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All outputs skew <100 ps typical (250 max.)
15 to 80 MHz output operation
Zero input to output delay
50% duty cycle outputs
Outputs drive 50惟 terminated lines
Low operating current
24-pin SOIC package
Jitter:<200 ps peak to peak, <25 ps RMS
The completely integrated PLL enables 鈥渮ero delay鈥?capability.
External divide capability, combined with the internal PLL, allows
distribution of a low frequency clock that is multiplied by virtually
any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock
speed and flexibility.
Block Diagram Description
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
Functional Description
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer
low skew system clock distribution. These multiple output clock
drivers optimize the timing of high performance computer
systems. Each of the eight individual drivers can drive terminated
transmission lines with impedances as low as 50惟. They deliver
minimal and specified output skews and full swing logic levels
(CY7B9910 TTL or CY7B9920 CMOS).
VCO
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency. The operational range of the VCO is
determined by the FS control pin.
Logic Block Diagram
TEST
FB
REF
FS
PHASE
FREQ
DET
VOLTAGE
FILTER
CONTROLLED
OSCILLATOR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cypress Semiconductor Corporation
Document Number: 38-07135 Rev. *B
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198 Champion Court
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San Jose
,
CA 95134-1709
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408-943-2600
Revised August 07, 2007
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